[SI-LIST] Re: MOS cap on chip for DECOUPLING
- From: Rajat Chauhan <rajat@xxxxxxxxxxxx>
- To: mike_bihan@xxxxxxxxxxxx
- Date: Thu, 24 Jul 2003 12:03:17 +0530
Hi BH,
I found a good link on MOS Capacitors.
"http://ece-www.colorado.edu/~bart/book/book/";, Check chapter-6 of this
book.
I myself have not gone through it nicely but check if this can help you.
Thanks
Rajat
Bi Han wrote:
>
> Thanks for everyone's valuable inputs.
>
> That's helpful for understand the mos caps. Because I may have to use it in
> high speed chip, Can anyone talk something about their high frequency
> property?
>
> Thanks!
> BH
>
> While some gurus have already contributed very good analysis on this issue,
> I would like to contribute to a more subtle one. For some process the N+
> diffusion connected to VCC or P+ connected to VSS may be a problem
> during ESD stress. The reason is the ESD current might be encouraged
> to flow into that diffusion from the substrate/Well and might burn the
> metal contact during ESD stress. This is layout dependent and you have
> to consult your process people about the appropiate layout design rules.
>
> Regards,
> Raymond
>
> Bi Han on 23/07/2003 18:50:13
>
> Please respond to mike_bihan@xxxxxxxxxxxx
>
> To: List` Si
> cc: (bcc: Raymond Leung/sdc)
>
> Subject: [SI-LIST] MOS cap on chip for DECOUPLING
>
> Hi, experts:
>
> In CMOS technology, what's the difference between using MOS cap as VCC
> decoupling in three different ways?
>
> 1. NMOS --> gate to VCC, other three nodes to VSS (inversion)
>
> 2. PMOS --> gate to VCC, other three nodes to VSS (accumulation)
>
> 3. PMOS --> gate to vss, other three nodes to VCC ( inversion)
>
> What's their difference in High frequency application such as high speed
> limiting amplifier?
>
> Thanks!
>
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--
___________________________
RAJAT CHAUHAN
TI-Banglore
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