[SI-LIST] MOS cap on chip for DECOUPLING

From: Bi Han <mike_bihan@xxxxxxxxxxxx>
To: List` Si <si-list@xxxxxxxxxxxxx>
Date: Wed, 23 Jul 2003 16:50:13 +0800 (CST)

Hi, experts:
 
In CMOS technology, what's the difference between using MOS cap  as VCC 
decoupling in three different ways?
 
1.  NMOS --> gate to VCC, other three nodes to VSS (inversion)
 
2. PMOS --> gate to VCC, other three nodes to VSS (accumulation)
 
3. PMOS --> gate to vss, other three nodes to VCC ( inversion)
 
What's their difference in High frequency application such as high speed 
limiting amplifier?
 
Thanks!
 


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[SI-LIST] MOS cap on chip for DECOUPLING

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