Hello,
as I was curious I did a short spec check:
I was wrong, with my assumption on synchronous PD entry in LPDDR4:
Power Down entry /exit is asynchronous to CLK
There are some somehow loose CKE timings, but e. g. CKE
maintained low until tCKE is satisfied ==> no ringback alowed
But I have not found and strict timing/length maching requirements
(assumning, that the length matching can not be that wrong, that the
timings that I have seen could be violated)
From a level point of view we deal with unterminated VIH/L(AC):
0.75/0.25* VDD2
Which in my opinion makes CKE even more critical than others. Any
over/undershoot and ringback need to be controlled much better then for
terminated signals.
I guess with ACC training Madhu was referring to some kind of Hyperlynx
feature and not to some standard SI simulation or physical training ?
In this case I guess the question is really to be addressed to a Mentor
FAE.
Just for SI simulation I would recommend to take a look to the CKE
signal in order to ensure there are no over/undershoots or ringbacks ..
I have to admit this is something I have not done on my own so far (just
assuming if CKE is routed as other signals it will work).
Best regards
Hermann
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Am 08.07.2019 um 18:56 schrieb Bhagwath, Nitin:
Hi Madhu,
Assuming you mean the Clock Enable signal (usually called CKE), this should
not be a part of the Vref training, and should be removed if added to the set
of signals used for Vref training.
CKE has a Vih/Vil threshold independent of Vref, and different from the other
Address signals.
If this is a HyperLynx specific question, it might be best to reach out to
the AE.
Regards,
-Nitin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Madhu KR (ERS-ESG), HCLTech
Sent: Monday, July 1, 2019 3:38 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] LPDDR4 _CE inclusion in simulation
Hi All
With the LPDDR4
Is CE the signal used for any ACC Training?
(I read through the JEDEC spec where that there is only mention of using CE
when writing trained values into Mode registers ) Since the CE is always
high, should it be a part of Simulation while simulating in Hyperlynx Or can
that be left out from ACC bunch If you include the VREF level is pushed up
and I am seeing violation in ACC.
With the same setup if it is omitted no violations observed In Eye Mask.
Thanks
Madhu
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