Hello Madhu,
sorry, I was a bit confused, so I hoped somebody else will jump in..
usually I'm familar with the Terms of the DRAM guys, but you used some
that I have never heard before..
I have not found any signal any signal CE in the LPDDR4 (or DDR4 Spec).
Can you clarify which signal you are referring too? CKE?
ACC Training: again searching for ACC in the spec only found "access",
"account", "accomplish", "accurate" .. do you refer to Address,
command, Control bus ?
(usually I call this CCA, as CA is standard for Command / Address, and I
just add Control in front .. when including CLock this is CCCA .. but
these are no "industry standard" terms..just my own wording..)
Assuming you refer to CKE, the question is, why do you mention it is
always high? Main purpose of CKE are to enable power down mode.
Just guessing (from Commodity spec) entry into power down with CKE goes
low is syncronous, but as then the clock receiver is disabled the exit
from power down is asyncronous.
For doing some command bus training for differen FSP CKE seems also used
in LPDDR4, but I did not check for the timing requirements.
Anyhow, just because of syncronous use of CKE for power down entry I
woud consider CKE as standard part of the control bus...
But maybe I missunderstood your questions, as I'm not sure about the
terminology you used..
Hermann
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Am 01.07.2019 um 12:38 schrieb Madhu KR (ERS-ESG), HCLTech:
Hi All
With the LPDDR4
Is CE the signal used for any ACC Training?
(I read through the JEDEC spec where that there is only mention of using CE
when writing trained values into Mode registers )
Since the CE is always high, should it be a part of Simulation while
simulating in Hyperlynx
Or can that be left out from ACC bunch
If you include the VREF level is pushed up and I am seeing violation in ACC.
With the same setup if it is omitted no violations observed In Eye Mask.
Thanks
Madhu
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