Hi Madhu,
Assuming you mean the Clock Enable signal (usually called CKE), this should not
be a part of the Vref training, and should be removed if added to the set of
signals used for Vref training.
CKE has a Vih/Vil threshold independent of Vref, and different from the other
Address signals.
If this is a HyperLynx specific question, it might be best to reach out to the
AE.
Regards,
-Nitin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Madhu KR (ERS-ESG), HCLTech
Sent: Monday, July 1, 2019 3:38 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] LPDDR4 _CE inclusion in simulation
Hi All
With the LPDDR4
Is CE the signal used for any ACC Training?
(I read through the JEDEC spec where that there is only mention of using CE
when writing trained values into Mode registers ) Since the CE is always high,
should it be a part of Simulation while simulating in Hyperlynx Or can that be
left out from ACC bunch If you include the VREF level is pushed up and I am
seeing violation in ACC.
With the same setup if it is omitted no violations observed In Eye Mask.
Thanks
Madhu
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