[SI-LIST] Re: LC filters on SDRAM signal lines
- From: "Beal, Weston" <Weston_Beal@xxxxxxxxxx>
- To: "David Carney (Neenah)" <David.Carney@xxxxxxxxxx>
- Date: Fri, 24 Jun 2011 20:59:22 +0000
Have you looked at the simpler and cheaper solution of series resistors in the
data lines? This might reduce overshoot and ringing enough to pass your design
constraints. You can easily simulate the memory signals and investigate the
effect of different termination and filters before committing to a board
re-spin.
Weston
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of David Carney (Neenah)
Sent: Friday, June 24, 2011 11:08 AM
To: steve weir
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: LC filters on SDRAM signal lines
To clarify, our problem is that the GSM module is picking up broadband noise
whose source is the processor SDRAM bus on the board that the GSM module is
attached to. The proposal is to filter the SDRAM data lines to reduce the high
frequency 869-894 MHz + content in these signals without affecting the useful
frequency content in these 75 MHz signals and wrecking the signal integrity or
timing on the SDRAM bus. Reducing this high frequency content should reduce
the amount of noise coupled in to the GSM receiver which is currently causing
it to have a higher than acceptable BER.
This is not necessarily a desirable solution to us since adding all these
filters is a challenge for space and redoing a lot of routing, but it has been
suggested that this is one of the most effective solutions.
I'm trying to figure out how to evaluate whether it will be effective and also
whether it will not wreck the SDRAM bus SI and timing.
It sounds like your suggestion is to look more closely at the PDN around the
SDRAM bus before considering filtering the data lines?
Thanks for the response.
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Friday, June 24, 2011 12:19 PM
To: David Carney (Neenah)
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] LC filters on SDRAM signal lines
The point of any filter is to separate signal energy from noise energy.
Before you can begin thinking about a filter you need to determine if the
offending noise is well outside your signal spectrum. If it is not,
then your only available option is to shield. That is assuming that
your problem is GSM pick-up on the signal lines. Even though your SDRAM
is only running a 75MHz clock, in order for the timing to be stable you will
have spectrum at least out to around 400MHz, which is close to half
of the GSM. You don't have much of a window between your required pass and
stop bands.
The GSM "buzz of death" can get directly into anything that acts as an antenna.
It also does bad things to PDNs. You need to have a hard look
at your PDN and your layout to see just where it is that the GSM noise is
coupling in. If you are lucky, you can fix this with some changes to
your bypass network. If you've got a poorly designed stack-up and layout where
GSM noise is for example directly coupling into your signal
returns, then you will have to address that.
Steve.
On 6/24/2011 8:47 AM, David Carney (Neenah) wrote:
> I'm working on an embedded product with a GSM cellular module. The
> module is picking up broadband noise in the GSM850 band (869-894 MHz)
at
> levels of approximately -90dBm to -100dBm from the board it is on.
The
> noise is causing BER levels that are too high (fails some tests). The
> source of the noise has been tracked to a processor SDRAM bus
interface
> running at 75 MHz clock frequency. This processor and SDRAM are
> physically close to the GSM module on the board. One of the many
> suggestions for mitigating this problem that we are considering is to
> add LC filters to all of the SDRAM data lines such as the following
> example parts:
>
>
> Murata NFM18PS105R0J3
>
(http://search.murata.co.jp/Ceramy/image/img/PDF/ENG/L0111S0111NFM18PS.p
> df)
>
> TDK MEA1608PH (http://www.tdk.co.jp/tefe02/e9621_mea_signal_1.pdf)
>
>
>
> These parts are recommended for LCD interfaces. Does anyone have
> experience using these on SDRAM interfaces? Is this an effective way
to
> solve the problem? What considerations do we need to account for in
> using them? Has anyone modeled these parts for signal integrity
> simulations? We have been told by Murata that no model is available.
> What modeling approach did you use?
>
>
>
> Thanks.
>
>
>
>
>
> David T. Carney P.E.
>
> Senior Design Engineer
>
> Plexus Engineering Solutions
>
> Neenah Design Center
>
> 920.751.5646
>
>
>
>
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--
Steve Weir
IPBLOX, LLC
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