[SI-LIST] Re: LC filters on SDRAM signal lines
- From: Jory McKinley <jory_mckinley@xxxxxxxxx>
- To: "David Carney \(Neenah\)" <David.Carney@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Fri, 24 Jun 2011 09:45:49 -0700 (PDT)
Hello David,
Do you have an understanding of where the noise is coupled to the SDRAM? I
would look at the power planes/returns as a possible coupling path in which
case
you could strategically place several power ferrite beads, the placement is
important in that you will want to get these power beads as close to the
receiver power as possible (simulation will be required). If the noise is
being
coupled at one end of your SRAM bus then you may be able to insert a chip
ferrite bead (such as a murata BLM02AG121SN1 or similar) be careful to simulate
with the bead in place as you will see some rise/fall/delay time degradation.
-Jory
________________________________
From: David Carney (Neenah) <David.Carney@xxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Fri, June 24, 2011 10:47:51 AM
Subject: [SI-LIST] LC filters on SDRAM signal lines
I'm working on an embedded product with a GSM cellular module. The
module is picking up broadband noise in the GSM850 band (869-894 MHz) at
levels of approximately -90dBm to -100dBm from the board it is on. The
noise is causing BER levels that are too high (fails some tests). The
source of the noise has been tracked to a processor SDRAM bus interface
running at 75 MHz clock frequency. This processor and SDRAM are
physically close to the GSM module on the board. One of the many
suggestions for mitigating this problem that we are considering is to
add LC filters to all of the SDRAM data lines such as the following
example parts:
Murata NFM18PS105R0J3
(http://search.murata.co.jp/Ceramy/image/img/PDF/ENG/L0111S0111NFM18PS.p
df)
TDK MEA1608PH (http://www.tdk.co.jp/tefe02/e9621_mea_signal_1.pdf)
These parts are recommended for LCD interfaces. Does anyone have
experience using these on SDRAM interfaces? Is this an effective way to
solve the problem? What considerations do we need to account for in
using them? Has anyone modeled these parts for signal integrity
simulations? We have been told by Murata that no model is available.
What modeling approach did you use?
Thanks.
David T. Carney P.E.
Senior Design Engineer
Plexus Engineering Solutions
Neenah Design Center
920.751.5646
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