[SI-LIST] Re: LC filters on SDRAM signal lines
- From: "N. Paul Taddonio" <paul.taddonio@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 27 Jun 2011 11:01:31 -0400
One more basic thing to address is your memory bus termination. Even if
your memory functions without them,
you may want to use them on a board that requires low noise.
Lines that are poorly terminated will ring or overshoot and this can
generate noise.
----- Original Message -----
From: "임동순" <dongsoon72.lim@xxxxxxxxxxx>
To: <David.Carney@xxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Saturday, June 25, 2011 10:57 AM
Subject: [SI-LIST] Re: LC filters on SDRAM signal lines
> In mobile phone, RF sensitivity problem due to memory interface noise is
> general. I think reducing processor and SDRAM I/O Buffer's driver strength
> by changing S/W may help improving BER and RF
> sensitivity. I do not know what kind of product you are designing.
> Another solution is adding shield can around processor and SDRAM, if you
> have some space in your product. It would be more sure solution.
>
> ---원본 메시지---
> 발신인 : David Carney (Neenah)
> 발신일자 : 2011/06/25 00:47 (GMT+09:00)
>
> I'm working on an embedded product with a GSM cellular module. The
> module is picking up broadband noise in the GSM850 band (869-894 MHz) at
> levels of approximately -90dBm to -100dBm from the board it is on. The
> noise is causing BER levels that are too high (fails some tests). The
> source of the noise has been tracked to a processor SDRAM bus interface
> running at 75 MHz clock frequency. This processor and SDRAM are
> physically close to the GSM module on the board. One of the many
> suggestions for mitigating this problem that we are considering is to
> add LC filters to all of the SDRAM data lines such as the following
> example parts:
>
>
> Murata NFM18PS105R0J3
> (http://search.murata.co.jp/Ceramy/image/img/PDF/ENG/L0111S0111NFM18PS.p
> df)
>
> TDK MEA1608PH (http://www.tdk.co.jp/tefe02/e9621_mea_signal_1.pdf)
>
>
>
> These parts are recommended for LCD interfaces. Does anyone have
> experience using these on SDRAM interfaces? Is this an effective way to
> solve the problem? What considerations do we need to account for in
> using them? Has anyone modeled these parts for signal integrity
> simulations? We have been told by Murata that no model is available.
> What modeling approach did you use?
>
>
>
> Thanks.
>
>
>
>
>
> David T. Carney P.E.
>
> Senior Design Engineer
>
> Plexus Engineering Solutions
>
> Neenah Design Center
>
> 920.751.5646
>
>
>
>
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