[SI-LIST] Impedance control with split ground planes
- From: Balaji S <Balaji.S@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 18 Apr 2006 20:18:16 +0530
Hello All,
I have a couple of queries:
I have a stack-up as given below
--------TOP
--------S1
--------VCC
--------GND
--------S2
--------BOTTOM
All high speed signals (SDRAM - 133MHz) are routed on S1.I have copper
pour on TOP and
BOTTOM layers. The component density is High on both the outer layers,
hence a solid plane is not obtained.
1. For controlled impedance calculations, do i consider the traces on S2
as striplines or Micro-strip lines?
2. Our Fabricator told us that, when doing the impedance measurement on
coupons, he will
be considering GND and BOTTOM layers as solid planes. Will not the
result be different in the actual board,
since the Copper on BOTTOM layer is not completely solid?
Thank you
With Regards
Balaji S
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
