[SI-LIST] Re: Impedance control with split ground planes
- From: Balaji S <Balaji.S@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 18 Apr 2006 23:55:55 +0530
Hi Ivor,
The reason i went for that stack-up is due to real estate problem.
The processor is a 0.5mm BGA. Since board is small in size, we had to go
Blind (4mil ) vias.
4mil vias has a aspect ratio of 1:1. Hence the inner layers needs to be
immdeiately after the outer layers.
The di-electric chosen between BOTTOM and S2 is 2.7mil (Maximum capable by
our Fabricator)
Regards
Balaji S
Ivor Bowden <ivorlist@xxxxxxxxxxx>
04/18/2006 11:23 PM
To
Balaji.S@xxxxxxxxxxxx
cc
Subject
Re: [SI-LIST] Re: Impedance control with split ground planes
Balaji,
Try TOP-VCC-S1-S2-GND-BOTTOM. That way you can treat S1 and S2 as
asymmetrical stripline, and TOP and BOTTOM as microstrip. Make sure
routing is perpendicular on S1 and S2 so traces don't crosstalk. Bypass
VCC-GND very well, especially at drivers and receivers, so the planes
are at similar AC reference. You can't really consider copper flood on a
component or signal layer as a plane, because it is not contiguous, it
will hurt SI as the impedances will change as the traces cross the
copper islands. Probably the S1/S2 traces will need to be thinner and
the TOP and BOTTOM traces will need to be wider, for the same
impedances. Good luck.
Ivor
> At 07:48 AM 4/18/2006, Balaji S wrote:
>> Hello All,
>> I have a couple of queries:
>> I have a stack-up as given below
>>
>> --------TOP
>> --------S1
>> --------VCC
>> --------GND
>> --------S2
>> --------BOTTOM
>>
>> All high speed signals (SDRAM - 133MHz) are routed on S1.I have copper
>> pour on TOP and
>> BOTTOM layers. The component density is High on both the outer layers,
>> hence a solid plane is not obtained.
>>
>> 1. For controlled impedance calculations, do i consider the traces on
S2
>> as striplines or Micro-strip lines?
>> 2. Our Fabricator told us that, when doing the impedance measurement on
>> coupons, he will
>> be considering GND and BOTTOM layers as solid planes. Will not the
>> result be different in the actual board,
>> since the Copper on BOTTOM layer is not completely solid?
>>
>> Thank you
>>
>> With Regards
>> Balaji S
>>
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