[SI-LIST] Re: Impedance control with split ground planes
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: Balaji.S@xxxxxxxxxxxx
- Date: Thu, 20 Apr 2006 08:57:12 -0400
Balaji,
To answer your original question (whether traces should/could be considered
as stripline or microstrip), as always, it depends. In your case it
depends on
the relative position of traces and voids on the surface. If you have a
trace
on one of your signal layers and the copper pour on the surface is not
solid,
it will have a few primary impacts on the traces: If you look at the cross
section at any given point and imagine it is extended along the traces
to create
a uniform section, non-infinite return-plane width will result in
increased impedance
and increased crosstalk. If you can maintain at least one times the plane
separation of planes (BOTTOM to GND in your case) on either side of the
traces, probably you are all right. More accurate answers can be obtained
from any 2D field solver which allows you to adjust the return-plane width.
You would need to check for this condition along all of your high-speed
traces.
If there are areas where you do not have the surface ground extending
sufficiently beyound your traces, IF this happened along a uniform section,
the result still might be OK. If the increased crosstalk on those
sections is
still within your allowed range, you can either simply live with the higher
trace impedance, or you might be able to compensate for that by making
the trace narrower in that section, unless you are already using the
narrowest
trace according to your manufacturing limits. If there are sections
where the
surface copper would not be above your traces at all (complete void), the
primary concern is crosstalk, the secondary concern and effect is trace
impedance.
In a real board design you probably have constantly changing plane overhang
width along your traces. I would check for areas where you cannot maintain
the plane overhang of a BOTTOM-GND separation value. If those sections
where you do not have the safe plane overhang are longer in propagation
delay than a fraction of your assumed risetimes, the impact probably will be
noticeable or significant on your finished board. To find out whether this
is just a noticeable difference versus significant/detrimental
difference, you
could do a 'simple' test. If you analyze your timing, crosstalk, and
overall
signal quality in two extreme cases: 1) assuming both planes are perfect
and intact, and 2) removing one of the planes completely, and you find
that your design is OK in both of these extreme cases, I would consider
your design safe. Otherwise it would require a much more tedious way,
outlined above.
Hope this helps.
Regards,
Istvan Novak
SUN Microsystems
Balaji S wrote:
>Hi Steve,
>A small correction. My high speed signals are routed on S2 ( and not on
>S1. typo).. Still is the design so flawed??
>
>Since due to microvias (aspect ratio 1:1) and cost constraint, we had to
>go 4 that stack-up.
>
>Any suggestions for improvement will definitely be welcome..
>
>Regards
>Balaji S
>
>
>
>steve weir <weirsi@xxxxxxxxxx>
>Sent by: si-list-bounce@xxxxxxxxxxxxx
>04/19/2006 07:30 PM
>Please respond to
>weirsi@xxxxxxxxxx
>
>
>To
>subramanian1683@xxxxxxxxx, si-list@xxxxxxxxxxxxx
>cc
>
>Subject
>[SI-LIST] Re: Impedance control with split ground planes
>
>
>
>
>
>
>Subbu, it means the design is severely flawed.
>
>Steve.
>At 06:44 AM 4/19/2006, Subramanian R wrote:
>
>
>>Hi Steve,
>>Balaji, that dog won't hunt.
>>
>>Sorry, i didn't get u. wht was ur meaning??
>>
>>Regards
>>Subbu
>>
>>On 4/18/06, steve weir <weirsi@xxxxxxxxxx> wrote:
>>
>>
>>>Balaji, that dog won't hunt.
>>>
>>>
>>>Steve.
>>>At 07:48 AM 4/18/2006, Balaji S wrote:
>>>
>>>
>>>>Hello All,
>>>>I have a couple of queries:
>>>>I have a stack-up as given below
>>>>
>>>>--------TOP
>>>>--------S1
>>>>--------VCC
>>>>--------GND
>>>>--------S2
>>>>--------BOTTOM
>>>>
>>>>All high speed signals (SDRAM - 133MHz) are routed on S1.I have
>>>>
>>>>
>copper
>
>
>>>>pour on TOP and
>>>>BOTTOM layers. The component density is High on both the outer
>>>>
>>>>
>layers,
>
>
>>>>hence a solid plane is not obtained.
>>>>
>>>>1. For controlled impedance calculations, do i consider the traces on
>>>>
>>>>
>S2
>
>
>>>>as striplines or Micro-strip lines?
>>>>2. Our Fabricator told us that, when doing the impedance measurement
>>>>
>>>>
>on
>
>
>>>>coupons, he will
>>>> be considering GND and BOTTOM layers as solid planes. Will not
>>>>
>>>>
>the
>
>
>>>>result be different in the actual board,
>>>> since the Copper on BOTTOM layer is not completely solid?
>>>>
>>>>Thank you
>>>>
>>>>With Regards
>>>>Balaji S
>>>>
>>>>
>>>>
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