[SI-LIST] Re: Impedance control with split ground planes
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Balaji.S@xxxxxxxxxxxx,si-list@xxxxxxxxxxxxx
- Date: Tue, 18 Apr 2006 09:13:30 -0700
Balaji, that dog won't hunt.
Steve.
At 07:48 AM 4/18/2006, Balaji S wrote:
>Hello All,
>I have a couple of queries:
>I have a stack-up as given below
>
>--------TOP
>--------S1
>--------VCC
>--------GND
>--------S2
>--------BOTTOM
>
>All high speed signals (SDRAM - 133MHz) are routed on S1.I have copper
>pour on TOP and
>BOTTOM layers. The component density is High on both the outer layers,
>hence a solid plane is not obtained.
>
>1. For controlled impedance calculations, do i consider the traces on S2
>as striplines or Micro-strip lines?
>2. Our Fabricator told us that, when doing the impedance measurement on
>coupons, he will
> be considering GND and BOTTOM layers as solid planes. Will not the
>result be different in the actual board,
> since the Copper on BOTTOM layer is not completely solid?
>
>Thank you
>
>With Regards
>Balaji S
>
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