[SI-LIST] Re: Gnd pours
- From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 30 Jul 2019 18:20:21 +0000
I don't know why a fab would charge more for etching away less copper
You are getting more copper, so you need to pay more for it... :-)
(just kidding)
Arpad
===========================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [
mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Bill Hargin
Sent: Tuesday, July 30, 2019 1:15 PM
To: bherd@xxxxxxxxxx; hakim.sellaoui@xxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Gnd pours
Hi Bill:
Good feedback. I don't know why a fab would charge more for etching away less
copper - since it results in less waste.
I have a name for your SI blog if you ever start one: "Herd Mentality."
Bill Hargin
Director of Everything
Z-zero ▪ Innovative PCB Stackup Design ▪ www.z-zero.com
billh@xxxxxxxxxx ▪ 425-301-4425 ▪ Skype: bill.hargin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf Of
Bil Herd
Sent: Tuesday, July 30, 2019 10:47 AM
To: billh@xxxxxxxxxx; hakim.sellaoui@xxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Gnd pours
When it comes to ground pours on the outer layers I decide whether I am doing
it for shielding (non-return path) or to help lower the impedance of the PDN,
or in rarer instances, capping a microstrip (part of a return path), etc.
If shielding, I look at stitching as you have mentioned, if PDN I look at the
PDN as a whole. Basically I look at every resulting copper polygon to decide
whether its shielding or adding an unnecessary risk. (If there is nothing to
shield on that part of the PCB, why risk something that resonates, etc)
My go-to books on this are still Henry Ott's books, for example sections
16.4 and some of the nearby chapters on the stackup in "Electromagnetic
Compatibility Engineering ".
I tend not to worry about copper balancing in small qty's as that's the
vendor's problem to solve, in large qty their problems become my problems and
so I get their input rather than find they added some copper on their own or
charge me more or the PCB has an issue in general.
Sorry if this doesn't help, I just like mentioning Mr. Ott's work. :)
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf Of
Bill Hargin
Sent: Tuesday, July 30, 2019 1:01 PM
To: hakim.sellaoui@xxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Gnd pours
Hi Hakim:
As long as you're using stitching, as you said, I don't know of an argument
against ground pours in a "subtractive" etching scenario.
Going beyond your patch antenna comment, copper pours can also provide a return
path for adjacent high-speed signals - and potential shielding for differential
radiation, if that's a concern.
As you said, this approach often gets used to balance copper in the stackup, as
well, which is a good thing.
I'd love to hear the counterpoint ... Maybe I'm overlooking something, but I'm
not thinking of one.
Bill Hargin
Director of Everything
Z-zero ▪ Innovative PCB Stackup Design ▪
http://www.z-zero.com
mailto:billh@xxxxxxxxxx ▪ 425-301-4425 ▪ Skype: bill.hargin
-----Original Message-----
From:
mailto:si-list-bounce@xxxxxxxxxxxxx
<
mailto:si-list-bounce@xxxxxxxxxxxxx> On Behalf Of Hakim Sellaoui
Sent: Tuesday, July 30, 2019 7:56 AM
To:
mailto:si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Gnd pours
Hello all,
What are your views on gnd pours in multi-layered PCBs (even on top/bottom),
assuming everything is stitched to lamda/8 or /10 etc.
I think it's better to have it as it would reduce the amount of etching the PCB
fab, and thus I'll get a board closer to what my given stackup.
Furthermore, in most cases the PCB adds copper balancing should I not add the
pours.
I understand there could be risks of creating patch antennas, but would this
not be mitigated with stitching?
Kind regards,
--
Hakim Sellaoui
Hardware Engineer
DisplayLink (UK) Limited
Tel: +44 (0)1223 443920
DD: +44 (0)1223 443943
Fax: +44 (0)1223 443921
E:
mailto:hakim.sellaoui@xxxxxxxxxxxxxxx<
mailto:hakim.sellaoui@xxxxxxxxxxxxxxx>
W:
http://www.displaylink.com/<
http://www.displaylink.com/>
140 Science Park, Milton Road,
Cambridge, CB4 0GF,
United Kingdom.
Registered in England No. 04811048
DisplayLink Corp.
A US incorporated company.
480 S. California Avenue Ste 305, Palo Alto, CA 94306, USA.
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