[SI-LIST] Re: Diif pair geometry trade offs
- From: "Powell, Jon N" <jon.n.powell@xxxxxxxxx>
- To: <wdowsley@xxxxxxxxx>, <vinu@xxxxxxxxx>, <leeritchey@xxxxxxxxxxxxx>
- Date: Sat, 16 Jun 2007 23:01:03 -0700
We seem to be discussing two different issues.
I thought we were talking about our signal moving from (say) the top
layer on a board to the bottom layer on a board. The signal stays ground
referenced, but we are now referenced to the bottom ground plane and not
the top ground plane. We would hope the 2 ground (reference) planes have
vias connecting them and would want to be sure that these ground plane
connect vias are close to our high speed signal layer change vias.=20
Presumably this issue would be exacerbated in very thick boards.
Regards,
Jon
Disclaimer:
The content of this message is my personal opinion only and although I
am an employee of Intel, the statements I make here in no way represent
Intel's position on the issue, nor am I authorized to speak on behalf of
Intel on this matter.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Bill Owsley
Sent: Friday, June 15, 2007 8:03 PM
To: vinu@xxxxxxxxx; leeritchey@xxxxxxxxxxxxx
Cc: Joel Brown; Ken Cantrell; si-list
Subject: [SI-LIST] Re: Diif pair geometry trade offs
I would go with Lee on this one. Deliberately designing a very good
PDS, (usually somewhat contrary to app notes and other common knowledge)
will reduce if not eliminate most of the common concerns. This
particular one, I understood to be a change from one side of a reference
plane to the other side of the same reference plane. Note I said
reference plane because the DC value assigned is of no consequence. Now
had the trace changed more than one layer or had just changed to the
other side and closer to more distant plane, then the coupling would be
stronger to that further, more distant plane. That is assuming equal
spacing of two signal layers between two reference planes then a trace
on one layer will couple about 2/3 to the closer plane and 1/3 to the
further plane. Since this is a field, I expect it to transfer energy
rather easily between the two reference planes and the trace, thus a
layer transistion to the other or opposite side of one of those two
reference
planes would not meet much impedance. ** By designing a well behaved
PDS means that there would also be a bypass/decoupling cap or two, or
more, within an appropriate distance for the freq's of interest as well
as the plane to plane capacitance to provide for a low impedance path
for the return. A well designed PDS provide multiple paths for currents
and thus a lower impedance for signal returns as well as any power
delivery and suppression of board resonances. In this context, as well
as any other I can think of at the moment, (late Friday nite and halfway
thru a bottle of wine) any set of planes that have a DC assignment is a
PDS whether it is a mother board or daughter board and some redhead
orphan stepboard, especially if there are traces routed over the planes.
Getting return currents across a connector between mother and daughter
is a fun exercise indeed. Dr. Bruce of the "Bruce Lee Show" has some
good info on that stuff. ps. The "Lee" just mentioned is also
the Lee in these notes. And Dr. Bruce is a column editor of the
Tidbits in the IEEE EMC magazine where Colin B. just had a short article
published that had something to do with differential pairs.
Now if any of you have gotten this far and have noted and taken
exception to any of a number of items tossed in for a lively discussion,
pick your favorite out and start a new thread on it. =20
Vinu, you could give your SI and EMC co-workers in RTP a call.
=20
Vinu Arumugham <vinu@xxxxxxxxx> wrote:
Lee,
Joel was asking about switching reference from one ground plane to=20
another ground plane (not a Vdd plane). So an appropriately placed=20
ground via for the return current is needed. The configuration Joel=20
describes could be on a passive daughter card with no PDS.
Thanks,
Vinu
Lee Ritchey wrote:
> Vinu,
>
> A well engineered power delivery system essentially shorts all of the
Vdd
> planes to the ground planes at all of the frequencies contained in the
> signals being created by the circuits drawing power from the PDS..
That is
> the mission of a voltage source. Therefore, there is a "short" circuit
> from plane to plane and that is the path for return current. When
people
> have trouble with this, it is usually traceable to the PDS design or
lack
> of design.
>
> Think about the seemingly arbitrary advice you get from applications
notes
> on how to select and place bypass capacitors. From this kind of
advice, it
> just luck when the PDS comes out right.
>
> Hope this helps.
>
> Lee Ritchey
>
>
>=20
>> [Original Message]
>> From: Vinu Arumugham=20
>> To:=20
>> Cc: Joel Brown ; Ken Cantrell
>>=20
> ; si-list=20
>=20
>> Date: 6/15/2007 2:05:55 PM
>> Subject: [SI-LIST] Re: Diif pair geometry trade offs
>>
>> Lee,
>> For the specific situation that Joel describes (reference changing
from=20
>> one ground plane to another), it is not clear to me how any power=20
>> delivery system would help.
>>
>> Thanks,
>> Vinu
>>
>>
>> Lee Ritchey wrote:
>>=20
>>> Joel,
>>>
>>> Why are you worried about decreasing the trace width. We do
thousands
>>>=20
> of10
>=20
>>> Gb/S diff pairs with 3.5 mil traces. As to ground vias for layer
>>>=20
> changing,
>=20
>>> if you have well engineered power delivery systems, the "return
>>>=20
> currents"
>=20
>>> will have no trouble changing layers without the need for ground
vias
>>> nearby.
>>>
>>> Lee Ritchey
>>> Speeding Edge
>>>
>>>
>>>=20
>>>=20
>>>> [Original Message]
>>>> From: Joel Brown=20
>>>> To: Ken Cantrell ; SI-List
>>>>=20
>>>>=20
>>>=20
>>>=20
>>>=20
>>>> Date: 6/14/2007 10:09:30 AM
>>>> Subject: [SI-LIST] Re: Diif pair geometry trade offs
>>>>
>>>> I just wanted to clarify a few things in my original post:
>>>>
>>>> There have been several suggestions to decrease the trace width to
>>>>=20
>>>>=20
>>> maintain
>>>=20
>>>=20
>>>> the same impedance with decreasing dielectric height. My traces are
>>>>=20
>>>>=20
>>> already
>>>=20
>>>=20
>>>> down to 4.8 mils and I don't want to go much smaller, that is why I
>>>>=20
> stated
>=20
>>>> that I would have to increase the gap between traces in a pair to
>>>>=20
> maintain
>=20
>>>> impedance.
>>>>
>>>> The 3x spacing refers to separation from one pair to another or
from
>>>>=20
> one
>=20
>>>> pair to a single ended trace, not the gap between the + and -
signal
>>>>=20
>>>>=20
>>> within
>>>=20
>>>=20
>>>> a pair.
>>>>
>>>> I also have a new question: If a diff pair changes layers from the
top
>>>>=20
>>>>=20
>>> layer
>>>=20
>>>=20
>>>> (microstrip) to layer 3 (stripline) should a ground via be placed
near
>>>>=20
> the
>=20
>>>> transition via? When the signal is on the top layer it will be
using
>>>>=20
>>>>=20
>>> layer 2
>>>=20
>>>=20
>>>> ground plane as the reference plane. When the signal is on inner
layer
>>>>=20
> 3
>=20
>>>>=20
>>>>=20
>>> it
>>>=20
>>>=20
>>>> will be using the ground plane on layers 2 and 4 as the reference
>>>>=20
> plane.=20
>=20
>>>> I do have Hyperlynx which will solve for impedance values but it
does
>>>>=20
> not
>=20
>>>> model return currents flowing through planes and vias.=20
>>>>
>>>> Thanks - Joel
>>>>
>>>>
>>>> -----Original Message-----
>>>> From: Ken Cantrell [mailto:Ken.Cantrell@xxxxxxxxxxxxxxxx]=20
>>>> Sent: Thursday, June 14, 2007 9:12 AM
>>>> To: joel@xxxxxxxxxx; SI-List
>>>> Subject: RE: [SI-LIST] Diif pair geometry trade offs
>>>>
>>>> Joel -
>>>> If you don't have a solver get one so that you can see the effects
>>>>=20
>>>>=20
>>> yourself.
>>>=20
>>>=20
>>>> I would also add that density is always an issue. If not now, it
will
>>>>=20
> be
>=20
>>>>=20
>>>>=20
>>> in
>>>=20
>>>=20
>>>> the future.
>>>> These are general, not specific, guidelines for operation <=3D
500MHz.
>>>> Minimize the dielectric height. The smaller the height the smaller
the
>>>> trace width can be, and the closer the diff pair line spacing can
be.=20
>>>>=20
> "In
>=20
>>>> order to do this I would have to increase the inter pair spacing to
>>>>=20
>>>>=20
>>> maintain
>>>=20
>>>=20
>>>> 100 ohms impedance". Reduce your trace width to maintain the same
>>>> single-ended impedance at the reduced dielectric height and see
what
>>>>=20
> you
>=20
>>>> come up with. You can also do trickier things to minimize the diff
>>>>=20
>>>>=20
>>> spacing
>>>=20
>>>=20
>>>> if you are only concerned about diff Z on that particular trace
layer.
>>>> Shrinking all dimensions is, in general, a good thing. You can
safely
>>>>=20
>>>>=20
>>> run 3
>>>=20
>>>=20
>>>> mil trace widths and not be concerned about IR losses as long as
your
>>>>=20
>>>>=20
>>> total
>>>=20
>>>=20
>>>> path length is less than 36" or so. Dielectric losses are not a
>>>>=20
> concern
>=20
>>>>=20
>>>>=20
>>> at
>>>=20
>>>=20
>>>> this point.
>>>> Noise coupling on the reference plane in this context is typically
not
>>>>=20
> an
>=20
>>>> issue for EMI or SI. You might want to increase the lane-to-lane
>>>>=20
> spacing
>=20
>>>>=20
>>>>=20
>>> to
>>>=20
>>>=20
>>>> some multiple of the line-to-line diff pair spacing for crosstalk
>>>>=20
> reasons
>=20
>>>> depending on your driver type and board geometry. I would be more
>>>>=20
>>>>=20
>>> concerned
>>>=20
>>>=20
>>>> about the number of vias/line and via lengths than reference plane
>>>>=20
>>>>=20
>>> currents.
>>>=20
>>>=20
>>>> The primary concern is length matching. There was a recent thread
>>>>=20
>>>>=20
>>> entitled
>>>=20
>>>=20
>>>> "matching within 1 mil" that discussed some aspects of this issue
that
>>>>=20
> you
>=20
>>>> might want to look at. Length matching directly effects the diff to
>>>>=20
>>>>=20
>>> common
>>>=20
>>>=20
>>>> mode conversion that you are concerned about. The rules for length
>>>>=20
>>>>=20
>>> matching
>>>=20
>>>=20
>>>> are ambiguous at best, and more research needs to be done in this
>>>>=20
> area. I
>=20
>>>> use no more than 5 deg of phase at the frequency of operation. 100
>>>>=20
> mils
>=20
>>>> matching (3 deg at 500MHz, er =3D 4.0)will work on =
Data/ADD/CMD/CTRL.
>>>>=20
>>>>=20
>>> Clocks
>>>=20
>>>=20
>>>> might have to be run tighter depending on the application.
Interface
>>>> requirements are given by the parts manufacturers in most cases.
Use
>>>>=20
> them
>=20
>>>> as guidelines. I often use Tech Support if I have any questions.
>>>>
>>>> Ken
>>>>
>>>> -----Original Message-----
>>>> From: si-list-bounce@xxxxxxxxxxxxx
>>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Joel Brown
>>>> Sent: Wednesday, June 13, 2007 12:46 PM
>>>> To: SI-List
>>>> Subject: [SI-LIST] Diif pair geometry trade offs
>>>>
>>>>
>>>> I am working with a layout that uses diff pairs routed as stripline
on
>>>> internal layers and micro strip on outer layers. These include PCI
>>>>=20
>>>>=20
>>> Express,
>>>=20
>>>=20
>>>> USB, LVDS, Ethernet.
>>>> There are guidelines I have read that recommend spacing between
pairs
>>>>=20
> and
>=20
>>>> between other signals should be at least 3x dielectric height for
>>>>=20
>>>>=20
>>> stripline
>>>=20
>>>=20
>>>> and 4x dielectric height for microstrip.
>>>>
>>>> I am using 13.5 mils dielectric height for the internal layers
which
>>>>=20
>>>>=20
>>> means I
>>>=20
>>>=20
>>>> need spacing of 40 mils.
>>>>
>>>> If I want to increase my routing density (decrease spacing) then I
>>>>=20
> would
>=20
>>>> need to decrease the dielectric height.
>>>>
>>>> In order to do this I would have to increase the inter pair spacing
to
>>>> maintain 100 ohms impedance which would reduce the inter pair
coupling
>>>>=20
> and
>=20
>>>> increase the coupling to the reference plane.
>>>>
>>>> This means more current would flow on the plane. My understanding
is
>>>>=20
> that
>=20
>>>> this plane current flows in a circular loop on the plane underneath
the
>>>>=20
>>>>=20
>>> diff
>>>=20
>>>=20
>>>> pair traces essentially cancelling itself out to some degree. My
>>>>=20
> question
>=20
>>>>=20
>>>>=20
>>> is
>>>=20
>>>=20
>>>> there any issue (EMI or other) with forcing more of the return
current
>>>>=20
> to
>=20
>>>> flow on the planes? If density was not an issue would it be
desirable
>>>>=20
> to
>=20
>>>> make the dielectric height as large as possible to reduce reference
>>>>=20
> plane
>=20
>>>> current?
>>>>
>>>>
>>>>
>>>> Thanks - Joel
>>>>
>>>>
>>>>
>>>>
>>>>
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