[SI-LIST] Re: Diif pair geometry trade offs
- From: Bill Owsley <wdowsley@xxxxxxxxx>
- To: joel@xxxxxxxxxx, 'Ken Cantrell' <Ken.Cantrell@xxxxxxxxxxxxxxxx>, 'SI-List' <si-list@xxxxxxxxxxxxx>
- Date: Thu, 14 Jun 2007 10:40:07 -0700 (PDT)
In ref. to your original question about currents in the reference plane, and
the second part of this note, since the reference plane is the larger copper
and lower impedance compared to the "other" trace of the diff pair, most of the
return current will flow in the reference plane. For the internal layer,
adding a connecting via/s near to the transition cannot hurt and is likely to
help. The coupling co-efficient, usually called k, will lower the impedance as
the traces are routed closer together and then you find yourself the area of
considering differential and common mode impedances all together, and the
various termination techniques. And to be sure, don't break the reference
plane below the traces. You can reduce the level of crosstalk between pairs by
adding a reference or ground trace as a guard trace between pairs, but then
that might not give you the density you want.
Joel Brown <joel@xxxxxxxxxx> wrote:
I just wanted to clarify a few things in my original post:
There have been several suggestions to decrease the trace width to maintain
the same impedance with decreasing dielectric height. My traces are already
down to 4.8 mils and I don't want to go much smaller, that is why I stated
that I would have to increase the gap between traces in a pair to maintain
impedance.
The 3x spacing refers to separation from one pair to another or from one
pair to a single ended trace, not the gap between the + and - signal within
a pair.
I also have a new question: If a diff pair changes layers from the top layer
(microstrip) to layer 3 (stripline) should a ground via be placed near the
transition via? When the signal is on the top layer it will be using layer 2
ground plane as the reference plane. When the signal is on inner layer 3 it
will be using the ground plane on layers 2 and 4 as the reference plane.
I do have Hyperlynx which will solve for impedance values but it does not
model return currents flowing through planes and vias.
Thanks - Joel
-----Original Message-----
From: Ken Cantrell [mailto:Ken.Cantrell@xxxxxxxxxxxxxxxx]
Sent: Thursday, June 14, 2007 9:12 AM
To: joel@xxxxxxxxxx; SI-List
Subject: RE: [SI-LIST] Diif pair geometry trade offs
Joel -
If you don't have a solver get one so that you can see the effects yourself.
I would also add that density is always an issue. If not now, it will be in
the future.
These are general, not specific, guidelines for operation <= 500MHz.
Minimize the dielectric height. The smaller the height the smaller the
trace width can be, and the closer the diff pair line spacing can be. "In
order to do this I would have to increase the inter pair spacing to maintain
100 ohms impedance". Reduce your trace width to maintain the same
single-ended impedance at the reduced dielectric height and see what you
come up with. You can also do trickier things to minimize the diff spacing
if you are only concerned about diff Z on that particular trace layer.
Shrinking all dimensions is, in general, a good thing. You can safely run 3
mil trace widths and not be concerned about IR losses as long as your total
path length is less than 36" or so. Dielectric losses are not a concern at
this point.
Noise coupling on the reference plane in this context is typically not an
issue for EMI or SI. You might want to increase the lane-to-lane spacing to
some multiple of the line-to-line diff pair spacing for crosstalk reasons
depending on your driver type and board geometry. I would be more concerned
about the number of vias/line and via lengths than reference plane currents.
The primary concern is length matching. There was a recent thread entitled
"matching within 1 mil" that discussed some aspects of this issue that you
might want to look at. Length matching directly effects the diff to common
mode conversion that you are concerned about. The rules for length matching
are ambiguous at best, and more research needs to be done in this area. I
use no more than 5 deg of phase at the frequency of operation. 100 mils
matching (3 deg at 500MHz, er = 4.0)will work on Data/ADD/CMD/CTRL. Clocks
might have to be run tighter depending on the application. Interface
requirements are given by the parts manufacturers in most cases. Use them
as guidelines. I often use Tech Support if I have any questions.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Joel Brown
Sent: Wednesday, June 13, 2007 12:46 PM
To: SI-List
Subject: [SI-LIST] Diif pair geometry trade offs
I am working with a layout that uses diff pairs routed as stripline on
internal layers and micro strip on outer layers. These include PCI Express,
USB, LVDS, Ethernet.
There are guidelines I have read that recommend spacing between pairs and
between other signals should be at least 3x dielectric height for stripline
and 4x dielectric height for microstrip.
I am using 13.5 mils dielectric height for the internal layers which means I
need spacing of 40 mils.
If I want to increase my routing density (decrease spacing) then I would
need to decrease the dielectric height.
In order to do this I would have to increase the inter pair spacing to
maintain 100 ohms impedance which would reduce the inter pair coupling and
increase the coupling to the reference plane.
This means more current would flow on the plane. My understanding is that
this plane current flows in a circular loop on the plane underneath the diff
pair traces essentially cancelling itself out to some degree. My question is
there any issue (EMI or other) with forcing more of the return current to
flow on the planes? If density was not an issue would it be desirable to
make the dielectric height as large as possible to reduce reference plane
current?
Thanks - Joel
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