[SI-LIST] Re: Diif pair geometry trade offs
- From: "Joel Brown" <joel@xxxxxxxxxx>
- To: <weirsi@xxxxxxxxxx>, <htc2rl@xxxxxxxxx>
- Date: Mon, 18 Jun 2007 10:07:31 -0700
I am wondering if a 3D field solver would give some insight into how return
currents flow on planes and through the PDS (stitching vias and bypass caps)
and what effect is has on the integrity of the signal. We currently do not
have a 3D solver but I might consider one if it would do this.
One thing that has not been discussed is how close the stitching vias need
to be to the signal via. I realize this is probably a complex subject which
would depend on the signal frequencies and board geometry. I am also
thinking that the return current flows through multiple vias that are
located on the vicinity of signal via. Again I see this where a 3D solver
may be of use. I am also guessing that folks who design IC packages may be
more advanced than board designers in terms of tools and techniques that
they use.
Joel
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of steve weir
Sent: Sunday, June 17, 2007 3:44 PM
To: htc2rl@xxxxxxxxx
Cc: si-list
Subject: [SI-LIST] Re: Diif pair geometry trade offs
Vadim, Lee, this is one of those hot-button topics that periodically
comes around. Usually a number of truisms get kicked around and in that
lies the danger for someone trying to map the experiences of others to
their situation. I would strongly recommend anyone interested in the
topic to go research any of the number of papers and reports out there
so that they can compare theory against anecdotal experiences and reduce
the problem to real numbers. Diffy pairs by themselves will be more
tolerant of return path discontinuities or even atrocities than
single-ended. When both high speed diffy pairs and wide single ended
busses share return paths through power cavities with significant
impedance within the power spectrum of particularly the single-ended
signals, interesting and unpleasant things can happen.
There are only two questions that I think anyone needs to ask to
determine what they need to do:
* What is the cross-talk budget cavity transitions for a given victim
signal?
* What is the impedance of the cavity(s) in the region where victim
signals make their transitions with respect to aggressor signals?
In defense of some of Lee's perspective:
* Diffy pairs launch from the package to the PCB usually near a field of
Vss balls from the package that attach all PCB layers of "gnd"
together. Whether they terminate at connectors or another IC usually
there is also a field of Vss stitch close by.
* Everywhere that a bypass capacitor exists on a PCB the "gnd" layers
are again stitched.
* Lee advocates a relatively even distribution of bypass capacitors over
the PCB, so there is never a very large distance from any signal
transition to a stitch via provided by the nearest bypass capacitor.
* The highest frequency signaling components, be they the diffy leading
edges, or RAM leading edges are for almost any PCB well beyond the point
where the PCB cavity dominates over the attached bypass network.
It shouldn't be hard to see from the above that using Lee's practices
all Vss layers are well-stitched and transitions between Vss references
will have a lot more to worry about from via stubs than from return path
discontinuities. The more controversial issue is whether a pair can be
routed against other rails. Lee states that "with the right PI design"
they can. And while that is true, the devil will always be in what "the
right PI design" entails as this involves both the signaling and power
design. It is easy to get this combination wrong and make a big mess.
When one cannot afford layers or arrange placement for contiguous Vss
referenced transmission lines, taking the time to find out if mixed
references will be adequate, and engineering the signaling and PI so
that they are can have big pay-offs in cost savings. The rising dollar
volume of digital consumer devices is pushing us more and more into
dealing with mixed voltages in return paths. So these are valuable
skills to acquire.
Regards,
Steve.
Vadim Heyfitch wrote:
> Actually there is solid evidence to the contrary: id does matter in
packages how far away is the nearest return current via to the signal via.
But maybe you bundled this under the broad stroke of "well engineered power
delivery systems"?
> -Vadim
>
>
> Lee Ritchey <leeritchey@xxxxxxxxxxxxx> wrote: Joel,
>
> Why are you worried about decreasing the trace width. We do thousands
of10
> Gb/S diff pairs with 3.5 mil traces. As to ground vias for layer
changing,
> if you have well engineered power delivery systems, the "return currents"
> will have no trouble changing layers without the need for ground vias
> nearby.
>
> Lee Ritchey
> Speeding Edge
>
>
>
>> [Original Message]
>> From: Joel Brown
>> To: Ken Cantrell ; SI-List
>>
>
>
>> Date: 6/14/2007 10:09:30 AM
>> Subject: [SI-LIST] Re: Diif pair geometry trade offs
>>
>> I just wanted to clarify a few things in my original post:
>>
>> There have been several suggestions to decrease the trace width to
>>
> maintain
>
>> the same impedance with decreasing dielectric height. My traces are
>>
> already
>
>> down to 4.8 mils and I don't want to go much smaller, that is why I
stated
>> that I would have to increase the gap between traces in a pair to
maintain
>> impedance.
>>
>> The 3x spacing refers to separation from one pair to another or from one
>> pair to a single ended trace, not the gap between the + and - signal
>>
> within
>
>> a pair.
>>
>> I also have a new question: If a diff pair changes layers from the top
>>
> layer
>
>> (microstrip) to layer 3 (stripline) should a ground via be placed near
the
>> transition via? When the signal is on the top layer it will be using
>>
> layer 2
>
>> ground plane as the reference plane. When the signal is on inner layer 3
>>
> it
>
>> will be using the ground plane on layers 2 and 4 as the reference plane.
>>
>> I do have Hyperlynx which will solve for impedance values but it does not
>> model return currents flowing through planes and vias.
>>
>> Thanks - Joel
>>
>>
>> -----Original Message-----
>> From: Ken Cantrell [mailto:Ken.Cantrell@xxxxxxxxxxxxxxxx]
>> Sent: Thursday, June 14, 2007 9:12 AM
>> To: joel@xxxxxxxxxx; SI-List
>> Subject: RE: [SI-LIST] Diif pair geometry trade offs
>>
>> Joel -
>> If you don't have a solver get one so that you can see the effects
>>
> yourself.
>
>> I would also add that density is always an issue. If not now, it will be
>>
> in
>
>> the future.
>> These are general, not specific, guidelines for operation <= 500MHz.
>> Minimize the dielectric height. The smaller the height the smaller the
>> trace width can be, and the closer the diff pair line spacing can be.
"In
>> order to do this I would have to increase the inter pair spacing to
>>
> maintain
>
>> 100 ohms impedance". Reduce your trace width to maintain the same
>> single-ended impedance at the reduced dielectric height and see what you
>> come up with. You can also do trickier things to minimize the diff
>>
> spacing
>
>> if you are only concerned about diff Z on that particular trace layer.
>> Shrinking all dimensions is, in general, a good thing. You can safely
>>
> run 3
>
>> mil trace widths and not be concerned about IR losses as long as your
>>
> total
>
>> path length is less than 36" or so. Dielectric losses are not a concern
>>
> at
>
>> this point.
>> Noise coupling on the reference plane in this context is typically not an
>> issue for EMI or SI. You might want to increase the lane-to-lane spacing
>>
> to
>
>> some multiple of the line-to-line diff pair spacing for crosstalk reasons
>> depending on your driver type and board geometry. I would be more
>>
> concerned
>
>> about the number of vias/line and via lengths than reference plane
>>
> currents.
>
>> The primary concern is length matching. There was a recent thread
>>
> entitled
>
>> "matching within 1 mil" that discussed some aspects of this issue that
you
>> might want to look at. Length matching directly effects the diff to
>>
> common
>
>> mode conversion that you are concerned about. The rules for length
>>
> matching
>
>> are ambiguous at best, and more research needs to be done in this area.
I
>> use no more than 5 deg of phase at the frequency of operation. 100 mils
>> matching (3 deg at 500MHz, er = 4.0)will work on Data/ADD/CMD/CTRL.
>>
> Clocks
>
>> might have to be run tighter depending on the application. Interface
>> requirements are given by the parts manufacturers in most cases. Use
them
>> as guidelines. I often use Tech Support if I have any questions.
>>
>> Ken
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Joel Brown
>> Sent: Wednesday, June 13, 2007 12:46 PM
>> To: SI-List
>> Subject: [SI-LIST] Diif pair geometry trade offs
>>
>>
>> I am working with a layout that uses diff pairs routed as stripline on
>> internal layers and micro strip on outer layers. These include PCI
>>
> Express,
>
>> USB, LVDS, Ethernet.
>> There are guidelines I have read that recommend spacing between pairs and
>> between other signals should be at least 3x dielectric height for
>>
> stripline
>
>> and 4x dielectric height for microstrip.
>>
>> I am using 13.5 mils dielectric height for the internal layers which
>>
> means I
>
>> need spacing of 40 mils.
>>
>> If I want to increase my routing density (decrease spacing) then I would
>> need to decrease the dielectric height.
>>
>> In order to do this I would have to increase the inter pair spacing to
>> maintain 100 ohms impedance which would reduce the inter pair coupling
and
>> increase the coupling to the reference plane.
>>
>> This means more current would flow on the plane. My understanding is that
>> this plane current flows in a circular loop on the plane underneath the
>>
> diff
>
>> pair traces essentially cancelling itself out to some degree. My question
>>
> is
>
>> there any issue (EMI or other) with forcing more of the return current to
>> flow on the planes? If density was not an issue would it be desirable to
>> make the dielectric height as large as possible to reduce reference plane
>> current?
>>
>>
>>
>> Thanks - Joel
>>
>>
>>
>>
>>
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