[SI-LIST] Re: Decoupling capacitors for BGA
- From: steve weir <weirsi@xxxxxxxxxx>
- To: mark.alexander@xxxxxxxxxx,"mark.alexander" <mark.alexander@xxxxxxxxxx>, <joepaulm@xxxxxxxxx>,<si-list@xxxxxxxxxxxxx>
- Date: Thu, 18 May 2006 05:01:40 -0700
Yes, if the work is doen from top to bottom then low cost is feasible.
Regards,
Steve.
At 11:52 AM 5/17/2006, Mark Alexander wrote:
>Steve,
>
>I don't think we disagree. I'm saying if the system design is done
>correctly (from the die to the network and everything in-between*) it's
>possible to do this stuff in only a few layers.
>
>-mark
>
>*may entail tremendous amounts of work
>
>=20
>
>-----Original Message-----
>From: steve weir [mailto:weirsi@xxxxxxxxxx]=20
>Sent: Wednesday, May 17, 2006 3:47 AM
>To: mark.alexander; joepaulm@xxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: Decoupling capacitors for BGA
>
>Mark, I disagree. All interconnects impose performance=20
>limits. Just because a product has cost constraints that dictate a=20
>low layer count board doesn't make such a design feasible.
>
>While we can realize robust designs in some cases even on 2 layers,=20
>the interconnect is typically a major limiting factor as to what we=20
>can do. On the other side is the chip that imposes demands on the=20
>interconnect. The minimum interconnect requirements are implicit in=20
>the chip implementation whether the chip designer realizes that fact=20
>or not. Chips can be engineered to work on low layer count boards,=20
>high layer count, or by afterthought engineering not in any=20
>realizable environment. FPGAs are unique in the amount of control the=20
>OEM has on the device requirements in a given application.
>
>Ask not what your interconnect can do for you. Ask what you can do=20
>for your interconnect.
>
>Regards,
>
>
>Steve.
>At 11:11 AM 5/16/2006, Mark Alexander wrote:
> >Joe,
> >
> >Additional layers certainly make good PDS design easier, but they're
>not
> >a necessity. Many applications are shoehorned into the 4-6 layer
>regime
> >by cost optimization, and the remarkable thing is that many of them
>have
> >good, robust PDS's -- they have to!
> >
> >The main idea here is that if you can throw layers at the problem, the
> >task of designing an adequate PDS is made much much simpler. If you
> >don't have the luxury of layers, you're forced into tradeoffs and
> >compromises and you have to do everything right; check every decision.
> >No room for mistakes.
> >
> >-mark
> >
> >
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
> >On Behalf Of Joe Paul M
> >Sent: Tuesday, May 16, 2006 4:25 AM
> >To: si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: Decoupling capacitors for BGA
> >
> >HI Subbu,
> >I saw the replies you got and the refernce docs they specified
> >They will give you a good idea on giving optimal decoupling.
> >
> >But ,
> >the 6 layer stack up you are using doesnt sound good to me.
> >I dont know , what is the kind of stack up you are using ,but if you
> >dont=3D20
> >have an an adjacent VCC-GND pair , you are inviting a lot of troubles.
> >
> >With a processor runningat 532 Mhz , I suggest you to improve the stack
> >up=3D20
> >to an 8 layer one ,with a pair of toughtly coupled VCC-GND layer pair.
> >According to me the cost you pay for the extra 2 layers is not much
>,=3D20
> >compared to the advantage it brings.
> >
> >Gurus: Please correct if I am wrong.
> >
> >Regards
> >Joe Paul
> >
> >
> >----- Original Message -----=3D20
> >From: "Subramanian R" <subramanian1683@xxxxxxxxx>
> >To: <si-list@xxxxxxxxxxxxx>
> >Sent: Friday, May 12, 2006 2:32 PM
> >Subject: [SI-LIST] Decoupling capacitors for BGA
> >
> >
> > > Hello All,
> > > We are using a 0.5mm Pitch 457-Pin BGA Processor. It is running at
>a=3D20
> > > maximum
> > > of 532MHz.
> > > It has 60 Power pins (Core & I/O)
> > >
> > > How do i place the Decoupling capacitors?
> > >
> > > Now we have placed all decaps (0402 pack) around the BGA (like an
> >island)
> > > and connected it to the VCC plane. Should i need to route it to the
> > > individual pins itself?
> > >
> > > The BGA does not have much space between the Balls. So not more than
> >4-5
> > > caps can be placed right over the BGA on the other side.
> > >
> > > The other thing i can go for is Inter-plane capacitance. But for
>that
> > > VCC-GND dielectric should be around 2-3mils, i understand. That
> >doesn't=3D20
> > > look
> > > possible with our PCB thickness requirements. It is a 6-layer PCB
> > >
> > > Thanks for any suggestions.
> > >
> > > Regards
> > > Subbu
> > >
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> > >=3D20
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