[SI-LIST] Re: DDRAM BUS Testing
- From: "Michael Rose" <mrose@xxxxxxxxxxxx>
- To: <Edi.Fraiman@xxxxxxxxxx>, "Vinu Arumugham" <vinu@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 2 Aug 2006 19:06:31 -0400
Edi,
I assume you're worried about signal integrity (not =
logic/functionality). Some troubleshooting tips to try:
1. measure noise on the Vref lines for both the FPGA and memory. I don't =
remember offhand but I belieive max is around 30mV. Micron Tech has a =
good DDR layout guide.
2. carefully measure 1.8V or 2.5V Vcc and Vtt noise (use an AC-coupled =
50 ohm coax soldered directly to a local bypass cap site.
3. Tie a probe to the DDR clock at the memory to trigger a high-speed =
scope (> 4GHz). It's nice to have software write a test loop to generate =
various read and write bit patterns on the memory bus (especially =
alternating 00s and FFs). Probe each memory line and note under/over =
shoot, jitter, Tsu and Th. Remember you have to probe D/DQ at the memory =
for write data and at the FPGA for read data.
4. For Xilinx FPGAs, pay particular attention to undershoot (see their =
appnote where they suggest running the memory bus drivers at .3V below =
Vcc to prevent reverse biasing the clamps).
I bet you'll find either excessive power supply noise, Vref noise, Vtt =
noise, or under/over shoot
Good Luck, Mike
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Fraiman, Edi
Sent: Wednesday, August 02, 2006 4:01 PM
To: Vinu Arumugham; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDRAM BUS Testing
Yes, FPGA support JTAG.
But JTAG frequency is low. JTAG test wasn't working because we are out
of spec (minimum DDR operating frequency).
=3D20
Best regards,
=3D20
Edi Fraiman
> -----Original Message-----
> From: Vinu Arumugham [mailto:vinu@xxxxxxxxx]=3D20
> Sent: Wednesday, August 02, 2006 3:54 PM
> To: Fraiman, Edi
> Subject: Re: [SI-LIST] DDRAM BUS Testing
>=3D20
>=3D20
> The FPGA does not support JTAG?
>=3D20
> Thanks,
> Vinu
>=3D20
> Fraiman, Edi wrote:
>=3D20
> >Hi,
> >=3D20
> >
> >I'm working on a design that includes FPGA with DDRAM controller =
and=3D20
> >several DDRAM chips. The traces goings direct from FPGA to=3D20
> DDRAM with=3D20
> >necessary pulll up resistor to Vref. (SSTL interface)=3D20
> without any debug=3D20
> >connector.
> >
> >=3D20
> >
> >Sometimes we have productions problems. It is very difficult to =
find=3D20
> >what bit in bus between FPGA and DDRAM is shorted or disconnected.
> >
> >Could somebody give any tips how it's possible debug DDRAM busses =
in=3D20
> >terms of production issues.
> >
> >=3D20
> >=3D20
> >Best regards,
> >=3D20
> >Edi Fraiman
> >=3D20
> >
> >
> > - - - - - Appended by Scientific Atlanta, a Cisco=3D20
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This e-mail and any attachments may contain information which is =
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