[SI-LIST] Re: DDRAM BUS Testing

  • From: "Fraiman, Edi" <Edi.Fraiman@xxxxxxxxxx>
  • To: "Vinu Arumugham" <vinu@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 2 Aug 2006 16:01:19 -0400

Yes, FPGA support JTAG.
But JTAG frequency is low. JTAG test wasn't working because we are out
of spec (minimum DDR operating frequency).

=20
Best regards,
=20
Edi Fraiman


> -----Original Message-----
> From: Vinu Arumugham [mailto:vinu@xxxxxxxxx]=20
> Sent: Wednesday, August 02, 2006 3:54 PM
> To: Fraiman, Edi
> Subject: Re: [SI-LIST] DDRAM BUS Testing
>=20
>=20
> The FPGA does not support JTAG?
>=20
> Thanks,
> Vinu
>=20
> Fraiman, Edi wrote:
>=20
> >Hi,
> >=20
> >
> >I'm working on a design that includes FPGA with DDRAM controller and=20
> >several DDRAM chips. The traces goings direct from FPGA to=20
> DDRAM with=20
> >necessary pulll up resistor to Vref. (SSTL interface)=20
> without any debug=20
> >connector.
> >
> >=20
> >
> >Sometimes we have productions problems. It is very difficult to find=20
> >what bit in bus between FPGA and DDRAM  is shorted or disconnected.
> >
> >Could somebody give any tips how it's possible debug DDRAM busses in=20
> >terms of production issues.
> >
> >=20
> >=20
> >Best regards,
> >=20
> >Edi Fraiman
> >=20
> >
> >
> >     - - - - - Appended by Scientific Atlanta, a Cisco=20
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>=20


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