[SI-LIST] Re: DDRAM BUS Testing
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Edi.Fraiman@xxxxxxxxxx,<si-list@xxxxxxxxxxxxx>
- Date: Wed, 02 Aug 2006 15:45:35 -0700
Edi, it depends on whose FPGA you are using, and how you configure your FPGA.
You could put test features into the FPGA design, as hard or
soft. Hard features are part of the functional design. Soft
features are test code that loads only when running diagnostics. The
DRAM can be tested at full speed.
You can incorporate test firmware from a host CPU. If the FPGA
includes CPU access to the DRAM this is often the simplest solution
to implement, but is slower than the solution above. If you are
doing basic bus checks, this is generally a non-issue.
You can test using JTAG.
Both Altera and Xilinx have both basic JTAG capability, as well as
support for embedded debugging using the JTAG for I/O. That leaves
open a lot of options even if you did not explicitly design for test.
Regards,
Steve.
At 12:30 PM 8/2/2006, Fraiman, Edi wrote:
>Hi,
>
>
>I'm working on a design that includes FPGA with DDRAM controller and
>several DDRAM chips. The traces goings direct from FPGA to DDRAM with
>necessary pulll up resistor to Vref. (SSTL interface) without any debug
>connector.
>
>
>
>Sometimes we have productions problems. It is very difficult to find
>what bit in bus between FPGA and DDRAM is shorted or disconnected.
>
>Could somebody give any tips how it's possible debug DDRAM busses in
>terms of production issues.
>
>
>
>Best regards,
>
>Edi Fraiman
>
>
>
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