[SI-LIST] Re: DDR3-1600 Double-Tee Topology
- From: Surjendra Goswami <goswamisurjendra@xxxxxxxxx>
- To: brian.p.moran@xxxxxxxxx
- Date: Tue, 14 Jan 2014 23:22:22 +0530
Joseph,
DDR3 supports write leveling and hence the fly-by topology is the most
prolific an DDR3 designs.
The double tee topology was used for DDR2 and had some downside in the
impedance discontinuities due to branching along the routes causing obvious
margin losses.
Regards
Surjendra
On Tue, Jan 14, 2014 at 10:25 PM, Moran, Brian P <brian.p.moran@xxxxxxxxx>wrote:
> Joseph,
>
> I have seen the Tee-Tee or the hybrid Tee-Daisy topology used in some
> instances. You are correct that the
> Tee-Tee is a pain to route and usually requires a type 4 MB. We do employ
> it in some LPDDR3 memory down
> configurations. In either case, it does require some impedance
> compensation between the main trunk and
> the tee branches in order to optimize. This is different than the tree
> topology used in DDR2, in that the length
> to all loads is matched. Where we found the Tee-Tee particularly
> interesting is when using multi-die pkgs. The
> daisy chain topology does not work well with high capacitance loads, such
> as you can have with LPDDR3 DDP
> and QDP devices. You can get excessive ledging and ringback in the first
> few nodes in the daisy chain. This is
> the reason the Tee-Tee topology was developed. However, if you are
> supporting only SDP
> devices then the daisy chain is the most straightforward.
>
> Brian Moran
> Memory Interface Technology
> Client Platforms
> Intel Corporation
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Joseph Aday
> Sent: Monday, January 13, 2014 6:07 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR3-1600 Double-Tee Topology
>
> Hi Everyone,
>
> Has
> anyone tried using a double-tee topology with their
> address/command/control signals in DDR3L/LPDDR3? This would be instead of
> the standard daisy-chain, with an Rtt at the end of the line.
>
> For example, take a controller with four memory nodes. It would look like
> this (think of DDR2 days):
>
> - RX
> - Branch -|
> | - RX TX ----------------- Rtt
> | - RX
> - Branch-|
> - RX
>
> To ensure matched timing for write leveling, this would even apply to the
> differential clock. I am doing memory-down (chips directly on the PWB as
> opposed to DIMMs.. if that matters?)
>
> Compared
> to a simple daisy chain, my simulations show this to be a bad idea both
> in eye diagram margins and in s-parameter plots. The double tee has less
> vertical / horizontal eye margin. The double-tee also has a resonant "suck
> out" in insertion loss very close to the clock frequency, whereas the
> standard daisy-chain is relatively flat out to 3GHz.
>
> Our
> chip vendor tells us this is needed to improve the eye diagram, but I
> can't see how or why. This is also a pain to route.. and so I have no good
> ideas as to why I should do this :)
>
> Am I missing something? Thoughts? Anyone else in the same boat? :)
>
> Thank you,
> Joseph Aday
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