[SI-LIST] Re: DDR3-1600 Double-Tee Topology

  • From: Hany Fahmy <hanymhfahmy@xxxxxxxxxxxxxxxxxxx>
  • To: "Liu, Bowen" <bowen.liu@xxxxxxxxx>
  • Date: Tue, 14 Jan 2014 19:49:47 +0100

Yep long time dear Bowen.
The output slew rate is very fast so w DDP, it actually smoothed out the
rising n falling creating nice eyes. W SDP, there is very strong ringback
due to fast slew rate that we csn make it working only when we add cterm by
Haswell pins. We don't have full control of output slew rate, that's why we
had to add Cterm like those old days , remember :)
On Jan 14, 2014 7:44 PM, "Liu, Bowen" <bowen.liu@xxxxxxxxx> wrote:

>  It’s nice to hear from you too, Fahmy.  J
>
> It is strange to see failure with SDP, but passing with DDP with Haswell.
>  It normally should be the other way around, as DDP has more loading which
> gives worse margin in general.
>
>
>
> Thanks,
>
> Bowen
>
> *From:* Hany Fahmy [mailto:hanymhfahmy@xxxxxxxxxxxxxxxxxxx]
> *Sent:* Tuesday, January 14, 2014 10:33 AM
> *To:* Liu, Bowen; goswamisurjendra@xxxxxxxxx; Moran, Brian P
> *Cc:* josephaday@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> *Subject:* RE: [SI-LIST] Re: DDR3-1600 Double-Tee Topology
>
>
>
> Hi Bowen. Long time man. We had a Recent case of a Haswell controller w
> memory down failing w SDP but passing w DDP using daisy chain. My point is
> that we can't generalize it n as u said u must simulate it especially for
> memory down cases.
>
>
>
> I think indeed the conclusion is : it must be simulated n as we onow it is
> also very sensitive to drver strength n output slew rate as well.
>
>
>
>
>
> Hany Fahmy
>
> CEO and Chief Consultant Officer
>
> Intelligent Solutions BVBA
>
> Http://www.intelligentsolutionsbvba.com
>
> +32471650724
>
> Sent from Samsung Mobile
>
>
>
>
> -------- Original message --------
> From: "Liu, Bowen" <bowen.liu@xxxxxxxxx>
> Date:
> To: goswamisurjendra@xxxxxxxxx,"Moran, Brian P" <brian.p.moran@xxxxxxxxx>
> Cc: josephaday@xxxxxxxxx,si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR3-1600 Double-Tee Topology
>
>
> Joseph,
> It depends on whether you are designing a system with SDP (single die
> package) or DDP (dual die package) DRAM devices.  If it is SDP, it doesn't
> matter which topology you use, both daisy-chain and double-T topologies
> should work fine for you, but if you are using DDP device, then double-T
> topology works better than daisy-chain in term of giving better system
> margin.  Even though daisy-chain topology (common for DDR3) can distribute
> load effect to improve margin, but it normally can cause some reflections
> among loads, and it is worse for DDP case.  I believe that's why DDR3/L
> RC-D (daisy-chain with DDP device) was only supported up to 1066MTs.  Like
> other people suggested, you can always run some simulation to verify which
> topology works better for you when you have doubts like this.
>
> Thanks,
> Bowen
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx 
> [mailto:si-list-bounce@xxxxxxxxxxxxx<si-list-bounce@xxxxxxxxxxxxx>]
> On Behalf Of Surjendra Goswami
> Sent: Tuesday, January 14, 2014 9:52 AM
> To: Moran, Brian P
> Cc: josephaday@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR3-1600 Double-Tee Topology
>
> Joseph,
> DDR3 supports write leveling  and hence the fly-by topology is the most
> prolific an DDR3 designs.
>
> The double tee topology was used for DDR2 and had some downside in the
> impedance discontinuities due to branching along the routes causing obvious
> margin losses.
>
> Regards
> Surjendra
>
>
> On Tue, Jan 14, 2014 at 10:25 PM, Moran, Brian P <brian.p.moran@xxxxxxxxx
> >wrote:
>
> > Joseph,
> >
> > I have seen the Tee-Tee or the hybrid Tee-Daisy topology used in some
> > instances.  You are correct that the Tee-Tee is a pain to route and
> > usually requires a type 4 MB.  We do employ it in some LPDDR3 memory
> > down configurations.  In either case, it does require some impedance
> > compensation between the main trunk and the tee branches in order to
> > optimize.  This is different than the tree topology used in DDR2, in
> > that the length to all loads is matched.  Where we found the Tee-Tee
> > particularly interesting is when using multi-die pkgs.  The daisy
> > chain topology does not work well with high capacitance loads, such as
> > you can have with LPDDR3 DDP and QDP devices.  You can get excessive
> > ledging and ringback in the first few nodes in the daisy chain. This
> > is the reason the Tee-Tee topology was developed.  However, if you are
> > supporting only SDP devices then the daisy chain is the most
> > straightforward.
> >
> > Brian Moran
> > Memory Interface Technology
> > Client Platforms
> > Intel Corporation
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx>]
> > On Behalf Of Joseph Aday
> > Sent: Monday, January 13, 2014 6:07 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] DDR3-1600 Double-Tee Topology
> >
> > Hi Everyone,
> >
> > Has
> >  anyone tried using a double-tee topology with their
> > address/command/control signals in DDR3L/LPDDR3?  This would be
> > instead of the standard daisy-chain, with an Rtt at the end of the line.
> >
> > For example, take a controller with four memory nodes.  It would look
> > like this (think of DDR2 days):
> >
> >                                           - RX
> >                          - Branch -|
> >                         |                  - RX TX ----------------- Rtt
> >                         |                 - RX
> >                          - Branch-|
> >                                           - RX
> >
> > To ensure matched timing for write leveling, this would even apply to
> > the differential clock.  I am doing memory-down (chips directly on the
> > PWB as opposed to DIMMs.. if that matters?)
> >
> > Compared
> >  to a simple daisy chain, my simulations show this to be a bad idea
> > both  in eye diagram margins and in s-parameter plots.  The double tee
> > has less vertical / horizontal eye margin.  The double-tee also has a
> > resonant "suck out" in insertion loss very close to the clock
> > frequency,  whereas the standard daisy-chain is relatively flat out to
> 3GHz.
> >
> > Our
> >  chip vendor tells us this is needed to improve the eye diagram, but I
> > can't see how or why.  This is also a pain to route.. and so I have no
> > good ideas as to why I should do this :)
> >
> > Am I missing something?  Thoughts?  Anyone else in the same boat? :)
> >
> > Thank you,
> > Joseph Aday
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