[SI-LIST] Re: DDR3-1600 Double-Tee Topology
- From: Joseph Aday <adayjoseph-lists@xxxxxxxxx>
- To: "mgreim001@xxxxxxxxx" <mgreim001@xxxxxxxxx>
- Date: Tue, 14 Jan 2014 21:29:06 -0800 (PST)
LOL! Thanks Michael
________________________________
From: Michael Greim <mgreim001@xxxxxxxxx>
To: josephaday@xxxxxxxxx
Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, January 14, 2014 9:26 AM
Subject: [SI-LIST] Re: DDR3-1600 Double-Tee Topology
Love to know who this vendor is.....;-)
going from DDR2 to DDR3 folks went fly by for a reason. I recommend making
them prove why ITHO a tree structure offers more margin than the fly by.
Micron has some great papers on point to point design on chip down
implementations. See if that offers any clarity.
Otherwise, I would recommend running sims both ways and showing why non
double T is the way to go. Trust but always verify.
Just my 0.02. Rambus way back when said I could do short or long channel
design and nothing else. They were wrong too, but then again I can be a SI
rebel at times.....;-)
-Michael.
We will either find a way or make one - Hannibal
In the middle of every difficulty lies opportunity - Al Einstein
If you think you can do something or you think
you can't, in both cases you are probably right - H Ford
And if I claim to be a wise man it surely means I'm paid too much......;-)
On Mon, Jan 13, 2014 at 8:06 PM, Joseph Aday <josephaday@xxxxxxxxx> wrote:
> Hi Everyone,
>
> Has
> anyone tried using a double-tee topology with their
> address/command/control signals in DDR3L/LPDDR3? This would be instead of
> the standard daisy-chain,
> with an Rtt at the end of the line.
>
> For example, take a controller with four memory nodes. It would look like
> this (think of DDR2 days):
>
> - RX
> - Branch -|
> | - RX
> TX ----------------- Rtt
> | - RX
> - Branch-|
> - RX
>
> To ensure matched timing for write leveling, this would even apply to the
> differential clock. I am doing memory-down (chips directly on the
> PWB as opposed to DIMMs.. if that matters?)
>
> Compared
> to a simple daisy chain, my simulations show this to be a bad idea both
> in eye diagram margins and in s-parameter plots. The double tee has
> less vertical / horizontal eye margin. The double-tee also has a
> resonant "suck out" in insertion loss very close to the clock frequency,
> whereas the standard daisy-chain is relatively flat out to 3GHz.
>
> Our
> chip vendor tells us this is needed to improve the eye diagram, but I
> can't see how or why. This is also a pain to route.. and so I have no
> good ideas as to why I should do this :)
>
> Am I missing something? Thoughts? Anyone else in the same boat? :)
>
> Thank you,
> Joseph Aday
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