[SI-LIST] DDR3-1600 Double-Tee Topology
- From: "Craciun, Liviu-Dumitru" <liviu-dumitru.craciun@xxxxxxxxxx>
- To: "'stefan.milnor@xxxxxxxxxxxxxx'" <stefan.milnor@xxxxxxxxxxxxxx>, "'adayjoseph-lists@xxxxxxxxx'" <adayjoseph-lists@xxxxxxxxx>, "'mgreim001@xxxxxxxxx'" <mgreim001@xxxxxxxxx>
- Date: Wed, 15 Jan 2014 10:58:50 +0100
The balanced-T topology is also possible and has the major advantage that it
doesn`t need termination if the driver strength is proper defined.
Normally needs the terminations a lot of PCB space and an extra power supply.
Both, PCB space and the components of the power supply means extra costs.
Best regards,
Liviu Craciun
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Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Milnor Stefan
Gesendet: Mittwoch, 15. Januar 2014 07:20
An: adayjoseph-lists@xxxxxxxxx; mgreim001@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Re: DDR3-1600 Double-Tee Topology
Regarding "who this vendor is" comment - I don't know, but I have seen the Tee
topology described for DDR3 use from two different Tier 1 SOC vendors that
everyone has heard of.
For one of the vendors, the application notes show the Tee topology and nothing
else. Perhaps their part or software does not support the wear leveling that
the daisy chain routing requires.
The other vendor described both the daisy chain and tee topologies, with an
emphasis on the daisy chain. The tee was offered for certain memory - down
configurations.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Joseph Aday
Sent: Tuesday, January 14, 2014 9:29 PM
To: mgreim001@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR3-1600 Double-Tee Topology
LOL! Thanks Michael
________________________________
From: Michael Greim <mgreim001@xxxxxxxxx>
To: josephaday@xxxxxxxxx
Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, January 14, 2014 9:26 AM
Subject: [SI-LIST] Re: DDR3-1600 Double-Tee Topology
Love to know who this vendor is.....;-)
going from DDR2 to DDR3 folks went fly by for a reason. I recommend making
them prove why ITHO a tree structure offers more margin than the fly by.
Micron has some great papers on point to point design on chip down
implementations. See if that offers any clarity.
Otherwise, I would recommend running sims both ways and showing why non double
T is the way to go. Trust but always verify.
Just my 0.02. Rambus way back when said I could do short or long channel
design and nothing else. They were wrong too, but then again I can be a SI
rebel at times.....;-)
-Michael.
We will either find a way or make one - Hannibal
In the middle of every difficulty lies opportunity - Al Einstein
If you think you can do something or you think you can't, in both cases you are
probably right - H Ford
And if I claim to be a wise man it surely means I'm paid too much......;-)
On Mon, Jan 13, 2014 at 8:06 PM, Joseph Aday <josephaday@xxxxxxxxx> wrote:
> Hi Everyone,
>
> Has
> anyone tried using a double-tee topology with their
>address/command/control signals in DDR3L/LPDDR3? This would be instead
>of the standard daisy-chain, with an Rtt at the end of the line.
>
> For example, take a controller with four memory nodes. It would look
> like this (think of DDR2 days):
>
> - RX
> - Branch -|
> | - RX TX -----------------
>Rtt
> | - RX
> - Branch-|
> - RX
>
> To ensure matched timing for write leveling, this would even apply to
> the differential clock. I am doing memory-down (chips directly on the
> PWB as opposed to DIMMs.. if that matters?)
>
> Compared
> to a simple daisy chain, my simulations show this to be a bad idea
>both
> in eye diagram margins and in s-parameter plots. The double tee has
>less vertical / horizontal eye margin. The double-tee also has a
>resonant "suck out" in insertion loss very close to the clock
>frequency,
> whereas the standard daisy-chain is relatively flat out to 3GHz.
>
> Our
> chip vendor tells us this is needed to improve the eye diagram, but I
>can't see how or why. This is also a pain to route.. and so I have no
>good ideas as to why I should do this :)
>
> Am I missing something? Thoughts? Anyone else in the same boat? :)
>
> Thank you,
> Joseph Aday
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