[SI-LIST] DDR3-1600 Double-Tee Topology
- From: Joseph Aday <josephaday@xxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 13 Jan 2014 18:06:57 -0800 (PST)
Hi Everyone,
Has
anyone tried using a double-tee topology with their
address/command/control signals in DDR3L/LPDDR3? This would be instead of the
standard daisy-chain,
with an Rtt at the end of the line.
For example, take a controller with four memory nodes. It would look like this
(think of DDR2 days):
- RX
- Branch -|
| - RX
TX ----------------- Rtt
| - RX
- Branch-|
- RX
To ensure matched timing for write leveling, this would even apply to the
differential clock. I am doing memory-down (chips directly on the
PWB as opposed to DIMMs.. if that matters?)
Compared
to a simple daisy chain, my simulations show this to be a bad idea both
in eye diagram margins and in s-parameter plots. The double tee has
less vertical / horizontal eye margin. The double-tee also has a
resonant "suck out" in insertion loss very close to the clock frequency,
whereas the standard daisy-chain is relatively flat out to 3GHz.
Our
chip vendor tells us this is needed to improve the eye diagram, but I
can't see how or why. This is also a pain to route.. and so I have no
good ideas as to why I should do this :)
Am I missing something? Thoughts? Anyone else in the same boat? :)
Thank you,
Joseph Aday
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