[SI-LIST] Re: DDR2 2-slot design preference...

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: leeritchey@xxxxxxxxxxxxx
  • Date: Mon, 29 Oct 2007 16:16:07 -0700

Lee, as the paper was presented in person, my recollection was that the 
board was said to fail.  The simulations did a quite reasonable job of 
predicting both the frequency of the resonances and their locality.  
Little surprise increasing stitch density in the offending areas quiets 
them down by pushing the resonance up above the signal content.  Whether 
that product was fixed for shipping by: stitching, moving victim 
antennae away from the hot area, or brute force shielding I do not 
know.  My understanding is that the cavity was GND-GND.

Rules of thumb are useful when they reliably reduce the amount of detail 
analysis needed to get to a successful result.  The danger is that RoT 
are often developed on the basis of perceived successes when they have 
little to do with root cause.  Worse they often then get misapplied to 
seemingly similar situations and to borrow a term of yours: they are 
really about as useful as elephant repellent to any real issues at 
hand.  In that case they are a bad substitute for proper analysis.  To 
get back to the case at hand, there are more and more people who are 
referencing GND only, and a single plane only out of a paranoid fear 
that going through any cavity with their signals will create real 
problems.  In many cases they are spending a lot on extra layers in 
their boards to keep those pesky elephants at bay.  The whole point here 
is quantify what is good enough so that unnecessary cost, or worse 
product spins and the associated product delays are avoided.

When it comes to coupling energy through a cavity it all comes down to 
numbers:  How much signal energy do we have in what spectrum, and how 
does that relate to where the cavity resonates and how badly the cavity 
resonates and what is the efficiency of the victim antennae.  If you 
want a test case that for example violates a specific threshold for one 
cavity configuration, and does not for another, it is just a matter of 
engineering to come up with the comparative cases.  Similarly, we can do 
the same thing for a defined level of signal impairment.  I am not sure 
who wants to finance that, but it could make a valuable demonstration 
for your classes.  If for example you wanted to determine how many DDR3 
lines could go through a given design power cavity before significant 
impairments develop, this is something that can be worked out.  But it 
does take the tools, accurate models, and the time to set the tools up 
and run them.  To form a complete picture with verification an 
appropriate test vehicle needs to be built and measured as well.

Best Regards,



Steve.


Lee Ritchey wrote:
> Steve,
>
> I have that paper and have read it.  It does not corellate from the tests
> made to any real EMI failures.   It just shows that ground stitching
> results in a difference.  There is a claim that this helpes solve a problem
> with a real product, but no data was presented.  (There are many such
> claims by EMI "Gurus" about their rules of thumb that turn out to be just
> that and this paper shows one, the 20H rule for one.) 
>
> Again, show me a real failure from cavity resonances, either functional or
> EMI not a simulation.
>
> Truman used to say  there are lies, damn lies and statistics.  In our
> profession there are lies, damn lies and unvalidated simulations, and, no,
> that paper does not demonstrate a direct correlation between the things
> simulated and real failures, just before and after differences.
>
> Lee
>
>
>   
>> [Original Message]
>> From: steve weir <weirsi@xxxxxxxxxx>
>> To: <leeritchey@xxxxxxxxxxxxx>
>> Cc: <Monji.Jabori@xxxxxx>; <si-list@xxxxxxxxxxxxx>
>> Date: 10/29/2007 10:27:21 AM
>> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
>>
>> Lee, the case at issue was a GND-GND cavity, but applies equally well 
>> for mixed voltages.  The physics are indisputable.  The issue is how bad 
>> does the problem have to be before we get:  a) EMI radiation, and EFT / 
>> ESD susceptibility, or b) signal integrity issues. 
>>
>> The good news is that until we get to ultrafast edge rates the simple 
>> remedy for the GND-GND case is simply stitch with sufficient density.  
>> That is becoming tougher for GND-VCC cavities, but can still be done in 
>> many cases.  It depends on just how much energy one wants injects into 
>> the cavity and what the spectrum of that energy looks like.
>>
>> For an example of a real-life case where adding stitching fixed a real 
>> problem get a hold of EMC2 / Ansoft paper delivered in Santa Clara just 
>> last week.  There you will see good correlation between both the models 
>> and the measurements demonstrating the phenomenon.  In their case the 
>> stitch was good enough for signaling but was generating an EMI issue.
>>
>> In the past few years the speed and accuracy of various simulation 
>> methods has improved immensely.  This permits designers to play what-if 
>> and get excellent performance without becoming slaves to ad-hoc rules.
>>
>> Best Regards,
>>
>>
>> Steve.
>>
>> Lee Ritchey wrote:
>>     
>>> I have heard many times about cavity resonances between power and ground
>>> planes being the source of problems.  However, I have yet to see any
>>>       
> clear
>   
>>> proof that such things happen and I have never seen a product fail from
>>> this in the design of 3000+ PCBs.  Could those who claim this happens
>>> please supply some evidence of this?  Not simulations, but actual
>>>       
> measured
>   
>>> results and not a statement that the last place it happened was at a
>>>       
> client
>   
>>> who has an NDA in place that prevents revealing the data.
>>>
>>> Lee Ritchey
>>>
>>>
>>>   
>>>       
>>>> [Original Message]
>>>> From: steve weir <weirsi@xxxxxxxxxx>
>>>> To: <Monji.Jabori@xxxxxx>
>>>> Cc: <si-list@xxxxxxxxxxxxx>
>>>> Date: 10/27/2007 2:09:16 PM
>>>> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
>>>>
>>>> Jabori, the issue in each case will be the resonant frequency of the
>>>>         
> GND 
>   
>>>> - GND cavity.  Stitch the cavity with an adequate via density to get
>>>>         
> the 
>   
>>>> resonance well above your signal energy and either topology can be
>>>>         
> made 
>   
>>>> to work well.
>>>>
>>>> Steve.
>>>> Jabori, Monji wrote:
>>>>     
>>>>         
>>>>> Hi Experts,
>>>>>  
>>>>>
>>>>> I am looking at two designs for a 2-slot DDR2-800 memory system. One
>>>>>           
> is
>   
>>>>> a butterfly design and the other has the slot on opposite sides of the
>>>>> motherboard (top and bottom).
>>>>>
>>>>> I am looking at the GND reference for both designs and have the
>>>>> following question knowing that I have to use GND referenced layers
>>>>>           
> for
>   
>>>>> each DDR2 channel.
>>>>>
>>>>>  
>>>>>
>>>>> For a butterfly design, my traces on an 8-layer design will flow from
>>>>> the memory controller via 2 internal layers with 2 different GND
>>>>>           
> layers,
>   
>>>>> i.e., one slot will have to change GND reference while the other will
>>>>> not.
>>>>>
>>>>>  
>>>>>
>>>>> In an opposite 2-slot design, however, we can make the traces that go
>>>>>           
> to
>   
>>>>> each internal layer have the same GND reference as the DIMM that is
>>>>> closer to it. For example, the Top DIMM will have the same GND
>>>>>           
> reference
>   
>>>>> (L2) as its channel traces coming on L3 while the Bottom DIMM will
>>>>>           
> have
>   
>>>>> its GND reference (L7) as its channel traces coming on L6.
>>>>>
>>>>>  
>>>>>
>>>>> Having said the above, would you guys prefer one design over another
>>>>> from an Signal Integrity point of view??
>>>>>
>>>>>  
>>>>>
>>>>> Thanks in advance.
>>>>>
>>>>>  
>>>>>
>>>>> Monji
>>>>>
>>>>>  
>>>>>
>>>>>  
>>>>>
>>>>>
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>>>>>
>>>>>
>>>>>
>>>>>   
>>>>>       
>>>>>           
>>>> -- 
>>>> Steve Weir
>>>> Teraspeed Consulting Group LLC 
>>>> 121 North River Drive 
>>>> Narragansett, RI 02882 
>>>>
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>>>>
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>>>
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>>>       
>> -- 
>> Steve Weir
>> Teraspeed Consulting Group LLC 
>> 121 North River Drive 
>> Narragansett, RI 02882 
>>
>> California office
>> (408) 884-3985 Business
>> (707) 780-1951 Fax
>>
>> Main office
>> (401) 284-1827 Business 
>> (401) 284-1840 Fax 
>>
>> Oregon office
>> (503) 430-1065 Business
>> (503) 430-1285 Fax
>>
>> http://www.teraspeed.com
>> This e-mail contains proprietary and confidential intellectual property
>>     
> of Teraspeed Consulting Group LLC
>   
> ----------------------------------------------------------------------------
> --------------------------
>   
>> Teraspeed(R) is the registered service mark of Teraspeed Consulting Group
>>     
> LLC
>   
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>   


-- 
Steve Weir
Teraspeed Consulting Group LLC 
121 North River Drive 
Narragansett, RI 02882 

California office
(408) 884-3985 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business 
(401) 284-1840 Fax 

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of 
Teraspeed Consulting Group LLC
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Teraspeed(R) is the registered service mark of Teraspeed Consulting Group LLC

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