[SI-LIST] Re: DDR2 2-slot design preference...
- From: steve weir <weirsi@xxxxxxxxxx>
- To: leeritchey@xxxxxxxxxxxxx
- Date: Mon, 29 Oct 2007 10:25:14 -0700
Lee, the case at issue was a GND-GND cavity, but applies equally well
for mixed voltages. The physics are indisputable. The issue is how bad
does the problem have to be before we get: a) EMI radiation, and EFT /
ESD susceptibility, or b) signal integrity issues.
The good news is that until we get to ultrafast edge rates the simple
remedy for the GND-GND case is simply stitch with sufficient density.
That is becoming tougher for GND-VCC cavities, but can still be done in
many cases. It depends on just how much energy one wants injects into
the cavity and what the spectrum of that energy looks like.
For an example of a real-life case where adding stitching fixed a real
problem get a hold of EMC2 / Ansoft paper delivered in Santa Clara just
last week. There you will see good correlation between both the models
and the measurements demonstrating the phenomenon. In their case the
stitch was good enough for signaling but was generating an EMI issue.
In the past few years the speed and accuracy of various simulation
methods has improved immensely. This permits designers to play what-if
and get excellent performance without becoming slaves to ad-hoc rules.
Best Regards,
Steve.
Lee Ritchey wrote:
> I have heard many times about cavity resonances between power and ground
> planes being the source of problems. However, I have yet to see any clear
> proof that such things happen and I have never seen a product fail from
> this in the design of 3000+ PCBs. Could those who claim this happens
> please supply some evidence of this? Not simulations, but actual measured
> results and not a statement that the last place it happened was at a client
> who has an NDA in place that prevents revealing the data.
>
> Lee Ritchey
>
>
>
>> [Original Message]
>> From: steve weir <weirsi@xxxxxxxxxx>
>> To: <Monji.Jabori@xxxxxx>
>> Cc: <si-list@xxxxxxxxxxxxx>
>> Date: 10/27/2007 2:09:16 PM
>> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
>>
>> Jabori, the issue in each case will be the resonant frequency of the GND
>> - GND cavity. Stitch the cavity with an adequate via density to get the
>> resonance well above your signal energy and either topology can be made
>> to work well.
>>
>> Steve.
>> Jabori, Monji wrote:
>>
>>> Hi Experts,
>>>
>>>
>>> I am looking at two designs for a 2-slot DDR2-800 memory system. One is
>>> a butterfly design and the other has the slot on opposite sides of the
>>> motherboard (top and bottom).
>>>
>>> I am looking at the GND reference for both designs and have the
>>> following question knowing that I have to use GND referenced layers for
>>> each DDR2 channel.
>>>
>>>
>>>
>>> For a butterfly design, my traces on an 8-layer design will flow from
>>> the memory controller via 2 internal layers with 2 different GND layers,
>>> i.e., one slot will have to change GND reference while the other will
>>> not.
>>>
>>>
>>>
>>> In an opposite 2-slot design, however, we can make the traces that go to
>>> each internal layer have the same GND reference as the DIMM that is
>>> closer to it. For example, the Top DIMM will have the same GND reference
>>> (L2) as its channel traces coming on L3 while the Bottom DIMM will have
>>> its GND reference (L7) as its channel traces coming on L6.
>>>
>>>
>>>
>>> Having said the above, would you guys prefer one design over another
>>> from an Signal Integrity point of view??
>>>
>>>
>>>
>>> Thanks in advance.
>>>
>>>
>>>
>>> Monji
>>>
>>>
>>>
>>>
>>>
>>>
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>> --
>> Steve Weir
>> Teraspeed Consulting Group LLC
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--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
California office
(408) 884-3985 Business
(707) 780-1951 Fax
Main office
(401) 284-1827 Business
(401) 284-1840 Fax
Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax
http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
Teraspeed Consulting Group LLC
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