[SI-LIST] Re: DDR2 2-slot design preference...
- From: "Eric Bogatin" <eric@xxxxxxxxxxxxxxx>
- To: "'Vinu Arumugham'" <vinu@xxxxxxxxx>
- Date: Wed, 31 Oct 2007 09:56:48 -0500
Vinu-
To add to Scott's response,
You are correct that the lumped model is not an accurate model for the via,
in the GHz bandwidth, however, it offers an instant estimate to the
magnitude of the noise to be expected, without having to spend 4 hours
setting up and running a 3D field solver.
As Scott articulated, the mode the signal travels in as it transitions from
the stripline to the non uniform path of the signal via and its return via,
is a combination of the twin wire- barrel transmission line- mode and the
cavity modes of the planes- this is how the energy gets transferred.
A single signal via and return via, passing through a bunch of cavity
layers, is sort of a dipole antenna that couples into the cavities. The
fields are not well confined to the signal and return vias, unless you
design them to be a coaxial geometry with multiple return vias around the
signal via. After all, how many magnetic field lines surround the return
conductor in a coax cable?
In the case of a differential stripline pair transitioning through two
signal vias to another diff stripline pair layer, even with a few return
vias, keep in mind that there is little cancellation of return currents in
the planes. As the differential signal transitions through the diff vias,
the return currents, which did not overlap in the planes, must find their
separate way to the other ref layers by coupling between planes and by
flowing through the one or two differential return vias.
To zeroth order, the return currents will spread out, overlap in their path
between the planes and cancel out. However, to first order, a fraction of
the return currents will take different paths and not cancel out, but
generate common signal noise.
In a typical case of 1 return via, there might easily by 20-50% of the
return current taking separate and distinct paths through the different
return conductors. Of course, the amount of overlap and the resulting common
signal that could couple into the cavity planes depends on the plane
spacings, via placements and layer transitions.
Unfortunately, this is one of those sorts of problems that is very difficult
to analyze by hand or with pencil and paper. It really requires a 3D field
solver that can take into account the frequency dependent current paths
based on the specific geometry. This makes it challenging to build intuition
about optimizing via designs.
--eric
**************************************
Dr. Eric Bogatin, President
Bogatin Enterprises, LLC
Setting the Standard for Signal Integrity Training
26235 w 110th terr
Olathe, KS 66061
v: 913-393-1305
f: 913-393-0929
c:913-424-4333
e:eric@xxxxxxxxxxxxxxx
www.BeTheSignal.com
Spring 2008 Signal Integrity Training Institute
EPSI, SIAA, BBDP
April 7-11, 2008, San Jose, CA
****************************************
-----Original Message-----
From: Vinu Arumugham [mailto:vinu@xxxxxxxxx]
Sent: Tuesday, October 30, 2007 6:54 PM
To: eric@xxxxxxxxxxxxxxx
Cc: pritchard_jason@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: DDR2 2-slot design preference...
Eric,
Unless I misunderstood, your description of the return via below does not
seem to be accurate.
The signal via and return via(s) form a transmission line. One can of course
tune the impedance of the signal via by changing the spacing and number of
return vias. I don't think it is accurate to use the lumped inductance value
and say that the return via has a series impedance of 6 ohm at 1GHz.
The noise injected into the planes by the return via(s) should be mostly
canceled due to the noise injected by the signal via.
"Keep in mind that a return via is not an ideal short. It has a finite
impedance. As a rough rule of thumb, its total inductance per length is
about 10 pH/mil. If the return via is 100 mils long, it has 1 nH of total
inductance. At 1 GHz, this is an impedance of 6 Ohms. If you have 1 return
via per signal via, the ground bounce across it, which would be a voltage
source, injecting noise into the planes, would be about 10% of the signal
swing voltage."
Thanks,
Vinu
Eric Bogatin wrote:
> Guys-
>
> I'll add two observations to this discussion on planes, vias and
resonances.
>
> I've been doing a lot of via design and simulation work with a 3D planar
> tool. I've had to re-adjust my intuition about the role of adjacent return
> vias and noise injection into cavities.
>
> As previously noted, the efficiency of injecting noise into the plane to
> plane cavity is related to the impedance of the cavity, which, to first
> order is about the spacing between the planes. The thinner the dielectric,
> the lower the impedance, and the less coupled energy driving the plane
> resonances.
>
> You get far more reduction in coupling to the cavity mode by thinner
> dielectric than by adding the return via. If the spacing between the
planes
> is thin, there is less vertical distance to couple between and the plane
> impedance is lower.
>
> In a large board, there will always be adjacent planes in the return path
> with a large spacing and this is the pair where cavity resonances will be
> excited.
>
> Secondly, having an adjacent return via does not suppress the coupling
into
> the cavity. It reduces it by maybe 50%, depending on the spacing to the
> signal via and its length. It is not enough to eliminate the noise
coupling
> into the plane to just have a return via adjacent to the signal via. You
may
> need a few. How many do you need? Of course, the answer is "it depends."
>
> The rule of thumb is best articulated by my good friend Frank Schonig who
> says, "A lot is good, more is better and too much is just right." I
haven't
> done the analysis, but I suspect that the more coaxial the return via
> arrangement looks to the signal via, the less total inductance in the
return
> path and the less the radiated coupling into the plane to plane cavity
> resonance.
>
> Of course it is not practical to add 4 return vias around each signal via,
> unless you are doing a very low density, high isolation board, like a test
> board or a load board. Everything else is going to be a compromise.
>
> If you are not going to do a detailed 3D planar simulation of the return
> plane stack up and the return via configuration to simulate how much
> insertion loss you loose into the planes, you will want to add design
> margin, like by adding vias along the edge, and multiple return vias in
> close proximity to the signal vias.
>
> Keep in mind that a return via is not an ideal short. It has a finite
> impedance. As a rough rule of thumb, its total inductance per length is
> about 10 pH/mil. If the return via is 100 mils long, it has 1 nH of total
> inductance. At 1 GHz, this is an impedance of 6 Ohms. If you have 1 return
> via per signal via, the ground bounce across it, which would be a voltage
> source, injecting noise into the planes, would be about 10% of the signal
> swing voltage.
>
> --eric
>
>
> **************************************
> Dr. Eric Bogatin, President
> Bogatin Enterprises, LLC
> Setting the Standard for Signal Integrity Training
> 26235 w 110th terr
> Olathe, KS 66061
> v: 913-393-1305
> f: 913-393-0929
> c:913-424-4333
> e:eric@xxxxxxxxxxxxxxx
> www.BeTheSignal.com
> Spring 2008 Signal Integrity Training Institute
> EPSI, SIAA, BBDP
> April 7-11, 2008, San Jose, CA
> ****************************************
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
> Behalf Of pritchard_jason@xxxxxxx
> Sent: Tuesday, October 30, 2007 1:58 PM
> To: Chris.Cheng@xxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
>
> Yes 1 ground via was placed directly next to each the signal vias on the
> test board. They were 100 ohm vias. Unfortunately it kept the impedance
> low at the edges of the via structure where the grounds were placed. You
> would need more ground vias to truly pin it down. We did one simulation
> with them taken out to show how it got worse.=20
>
> I would imagine voltage planes are more often the culprit for
> resonances. They may be only used to supply power at one location on the
> board and then are routed to the rest of the design as a signal
> reference. These planes typically don't have capacitors placed across
> the whole design. If you did have capacitors across the whole design you
> may only have a limited frequency range in which that may be effective.=20
>
> -Jason
>
>
>
> -----Original Message-----
> From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxx]=20
> Sent: Tuesday, October 30, 2007 2:40 PM
> To: pritchard, jason; si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: DDR2 2-slot design preference...
>
> Before I started I have to say I am also a big fan of ground via
> stitching around edges of PCB.
> That said. In your experiment, did you provide ground return current
> vias near your differential pair transition via ? One can easily design
> an experiment where return current path is denied (no ground vias near
> the signal vias) and it is forced to return through plane coupling (i.e.
> to justify thin core capacitance planes) or your via stitching (to
> contain the large EMI radiation field). Neither is the correct solution
> to the problem which is lack of return current vias.
> Another thing to consider is in real live non-backplane PCB's, there are
> tens of thousands of ground vias by IC's and passive components
> sprinkled around the PCB, it will be hard to find a large piece of
> via-less plane to start your resonance.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of
> pritchard_jason@xxxxxxx
> Sent: Tuesday, October 30, 2007 10:32 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR2 2-slot design preference...
>
>
> I contributed to the paper, so I'll try and shed some light on what was
> in it...
>
> The purpose of the paper was to explain how high frequency energy can
> travel across a PCB and radiate from PCB edges or end up in areas you
> didn't expect it to be.=3D20
>
> If you spend a little time in the lab taking EMI measurements then you
> will find out that if you take any board with high speed serial links
> with via transitions or stripline routing, and measure around the edge
> of the PCB you will almost always find energy there. The question I
> always had was, how did it get there? I have been doing SI for many
> years so I typically thought about problems in 2 dimensions. The problem
> with EMI is it's 3 dimensional. It is sometimes difficult to predict how
> energy will travel. The first step is knowing the mechanisms in which
> energy gets diverted and spread out across the PCB.=3D20
>
> The first thing we did was set-up simple experiments in SI-Wave to try
> and figure out what was going on. We created simplified etch layouts of
> the real board that was having problems. We soon came to the conclusion
> that via transitions were exciting resonances on the PCB. What we
> determined was that the size of your reference plane and the resultant
> cavity resonances created between 2 planes caused energy to travel in
> the direction of the resonances when excited by via transitions. This
> loss of energy to the planes can also be seen in the s-parameters of the
> etch. That is essentially the first half of the paper.=3D20
>
> We then went into the lab. The experiments were done on a backplane test
> board. It only had ground planes. We chose this board because it had SMA
> connections and allowed us the flexibility to apply whatever input we
> wanted. It also had the same etch/via structures of our problem board,
> and proves the point that it doesn't matter if its power or ground. All
> you need is 2 metal pieces to create a cavity resonator.=3D20
>
> The simulations and lab measurements proved that you could predict where
> emissions would occur on a PCB. Did this experiment actually solve a
> real problem? Indirectly. Once we knew what mechanisms allowed energy to
> go to unwanted places on a PCB you can change the layout to accommodate
> this. One solution is to use via stitching along the edge of the PCB to
> reduce the impedance so that it cant radiate. This was implemented
> because the board slipped into metal clips at the edges of the PCB. If
> you can squelch the noise before it gets to the metal clips you can
> reduce the amount of energy directly coupled to the chassis. Another
> solution would be to make sure your return path impedance is very low
> along all of your high speed signals which is very difficult in high
> density boards.=3D20
>
> You could consider via fencing along the edge of a PCB a "rule of
> thumb", but it's a useful one because I have yet to see anyone capable
> of looking at a PCB and tell me how the energy is going to travel across
> the PCB, couple, and radiate. This is not a 2D SI problem its 3D.
> Obviously you could put the work in and simulate it, but that is often
> time consuming and not available to most people.=3D20
>
> We were going to present the REAL board results at design con in
> February but it wasn't in the cards this year.=3D20
>
> I am not an EMI "guru". I just wanted to understand what is happening.
> Just because you haven't seen it doesn't mean it doesn't exist.=3D20
>
> References:=3D20
> * Reducing Simultaneous switching noise and emi on ground/power planes
> by dissipative edge termination. Istvan
> * EMI mitigation with multilayer Power Bus Stacks and via stitching of
> reference planes. Xiaoning ye, David M. Hockanson, Min Li,.....
> * Radiated Emission from a multilayer PCB with traces placed between
> power/ground planes. Takashi Harada, Hideki Sasaki, Toshihide Kuriyama
> * Reduction in radiated emission by symmetrical power-ground layer
> stack-up pcb no open edge. Satoru Haga, Ken Nakano, Osamu Hashimoto
> * The Radiation of a rectangular power bus structure at multiple cavity
> mode resonances. Marco Leone
> * Coupling of through hole signal via to power/ground references and
> excitation of edge radiation in multilayer PCB. Jun So Pak, Jingook Kim
> .....
>
> -Jason
>
>
>
>
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