[SI-LIST] Re: DDR interface
- From: "Fraiman, Edi" <Edi.Fraiman@xxxxxxxxxx>
- To: "preetesh rathod" <preeteshrathod@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 27 Sep 2006 10:32:00 -0400
You have to be more accurate.
Tdqss is time between "write" command (of course with clock edge) and
first DQS rising edge.
Best regards,
Edi Fraiman
-----Original Message-----
From: preetesh rathod [mailto:preeteshrathod@xxxxxxxxxxx]
Sent: Wednesday, September 27, 2006 6:39 AM
To: Fraiman, Edi; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: DDR interface
Time - DQS valid prior to CLK edge & DQS valid after clock edge
you can obtain from memory controller's datasheet.
Regards
Preetesh
preetesh rathod <preeteshrathod@xxxxxxxxxxx> wrote:
Hi
Yes You need to note tDQSS time in your DDR SDRAM.Note
time for DQS valid prior to Clk edge & DQS valid after clock edge(For
write). Find out time difference. From this time difference you can find
theoretical maximum & minimum length of DQS with respect to clock.
Thanks & Regards
Preetesh
"Fraiman, Edi" wrote:
Hi,
Yes you right. Actually JEDEC specify relatively wide
range : from 75%
to 125% of clock cycle.
Best regards,
Edi Fraiman
-----Original Message-----
From: Karthik Raj [mailto:karthikraj.g@xxxxxxxxx]
Sent: Tuesday, September 26, 2006 10:30 AM
To: Fraiman, Edi
Subject: Re: [SI-LIST] DDR interface
Hi,
I am not very sure about DDR but in DDR2 there is a spec
that
determines the CLK - DQS relation called tDQSS. You may
need to make
sure that your lengths meet this timing.
Rgds,
Karthik
On 9/26/06, Fraiman, Edi wrote:
Hi all,
I have question about DDR interface layout.
I understand that during PCB layout the DQS (data
strobe) should be
routed with same length as DQ (data), DQM signals and
Address bus and control signals (RAS,CAS, CKE,WE,CS)
should be aligned
to clock.
But I do not understand what relationship (what the
maximum difference
in length) between DQS and CLOCK.
Could you please advise?
=20
Best regards,
Edi Fraiman
=20
=20
=20
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