[SI-LIST] Re: DDR interface
- From: "Peterson, James F \(EHCOE\)" <james.f.peterson@xxxxxxxxxxxxx>
- To: <preeteshrathod@xxxxxxxxxxx>, "Fraiman, Edi" <Edi.Fraiman@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 28 Sep 2006 06:33:27 -0500
...and the reason for this 75%-125% relationship? my guess is to
confidently migrate data from the DQS clock domain to the CK clock
domain inside the SDRAM. (remember that no amount of double registering
will ever solve this type of problem. if you don't want to drop bits you
have to predict exactly where you can safely cross domains, and a way to
do that is to constrain the relationship between the two clocks.)
Jim
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of preetesh rathod
Sent: Thursday, September 28, 2006 1:01 AM
To: Fraiman, Edi; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR interface
Tdqss is specified normally as 75% to 125% of Tck i.e if TCK is 7.5ns.
then 75% -> 5.625ns & 125% -> 9.375ns. which in turn means that your DQS
edge must get valid (at DDR SDRAM) in time of 1.875ns prior to clock
edge & 1.875ns after clock edge. In memory controller datasheet there
must a parameter specifying DQS valid time before clock edge & DQS valid
after clock edge. Using these timimg parameter you can find out
theoretical maximum & minimum length for DQS signal with respect to
Clock.
=20
Regards
Preetesh
"Fraiman, Edi" <Edi.Fraiman@xxxxxxxxxx> wrote:
You have to be more accurate.
Tdqss is time between "write" command (of course with clock edge) and
first DQS rising edge.
=20
=20
=20
Best regards,
Edi Fraiman
=20
=20
=20
=20
-----Original Message-----
From: preetesh rathod [mailto:preeteshrathod@xxxxxxxxxxx]
Sent: Wednesday, September 27, 2006 6:39 AM
To: Fraiman, Edi; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: DDR interface
Time - DQS valid prior to CLK edge & DQS valid after clock edge you
can obtain from memory controller's datasheet.
=20
Regards
Preetesh=20
preetesh rathod <preeteshrathod@xxxxxxxxxxx> wrote:
Hi
Yes You need to note tDQSS time in your DDR SDRAM.Note time for DQS
valid prior to Clk edge & DQS valid after clock edge(For write). Find
out time difference. From this time difference you can find theoretical
maximum & minimum length of DQS with respect to clock.
Thanks & Regards
Preetesh
"Fraiman, Edi" wrote:
Hi,
Yes you right. Actually JEDEC specify relatively wide range : from 75%
to 125% of clock cycle.
Best regards,
Edi Fraiman
-----Original Message-----
From: Karthik Raj [mailto:karthikraj.g@xxxxxxxxx]=20
Sent: Tuesday, September 26, 2006 10:30 AM
To: Fraiman, Edi
Subject: Re: [SI-LIST] DDR interface
Hi,
I am not very sure about DDR but in DDR2 there is a spec that
determines the CLK - DQS relation called tDQSS. You may need to make
sure that your lengths meet this timing.
Rgds,
Karthik
On 9/26/06, Fraiman, Edi wrote:=20
Hi all,
I have question about DDR interface layout.
I understand that during PCB layout the DQS (data
strobe) should be=20
routed with same length as DQ (data), DQM signals and
Address bus and control signals (RAS,CAS, CKE,WE,CS)
should be aligned
to clock.
But I do not understand what relationship (what the
maximum difference
in length) between DQS and CLOCK.
Could you please advise?
=3D20
Best regards,
Edi Fraiman
=3D20
=3D20
=3D20
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