[SI-LIST] Re: DDR interface
- From: "Alex Li" <AlexLi@xxxxxxxxxxxx>
- To: <Edi.Fraiman@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 27 Sep 2006 09:54:54 +0800
Hi, Edi:
On DDR layout, you can routing DQS/DQ(DM)/Clock with same lengrh.
=20
On DDR2 layout, you can routing DQS and Clock with same length.
But data and data mask must be shorter than DQS
=20
B.R.
Alex Li
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Fraiman, Edi
Sent: Tuesday, September 26, 2006 9:50 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR interface
Hi all,
I have question about DDR interface layout.
I understand that during PCB layout the DQS (data strobe) should be
routed with same length as DQ (data), DQM signals and
Address bus and control signals (RAS,CAS, CKE,WE,CS) should be aligned
to clock.
But I do not understand what relationship (what the maximum difference
in length) between DQS and CLOCK.
Could you please advise?
=3D20
Best regards,
Edi Fraiman
=3D20
=3D20
=3D20
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