[SI-LIST] Re: Rise time impact on input buffer
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: "silist" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 27 Sep 2006 09:31:53 -0400
> One of my guess is Slow rise (long) time signal will dissipate more
> power in
> the buffer stage of CMOS IC and leads to metastability in the next
> stage. Is
> my guess correct?
Maximum rise times are especially important for clock inputs (such as the
example you gave), because slow edges are more susceptible to noise pickup
which may cause double-clocking inside the IC. Multiple edges received from
non-clock signals are often unimportant (as long as the earliest and latest
possible edges meet the other timing requirements), but metastability should
be considered.
Greater heat dissipation may happen but I believe it is usually not an
issue.
Inputs with hysteresis (Schmitt-triggered circuits) can be used when inputs
need to handle signals with slow transition times.
Regards,
Andy
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