[SI-LIST] Re: Copper Fill
- From: "George Tang" <gtang@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 14 Jun 2002 19:24:12 -0700
There have been a lot of good comments given by all. I would like to add a
few more points:
1. It has been established that routing single ended signal under copper
fill can cause signal integrity problems on the single ended signal or half
wave resonances on the copper patch. But there seems to be a belief that it
is ok for differential signals to go under copper fill areas. We know that
it is bad to route signals across a plane cut. It is not as severe a
problem if a differential pair is routed across a plane cut, *as long as the
cut is small compared to the signal rise time*. But if the cut is wide
compared to the signal rise-time, reflections will occur due to impedance
mismatches. The same is true with copper fills. If the fill is large
compared to the signal rise time, even differential signals will have
reflections when they are routed under the copper fill.
2. A few people mentioned that these copper patches should be made small to
avoid resonances under these patches, which may cause emi problems (or even
signal integrity problems if the resonance is coupled onto sensitive analog
circuits nearby). This is true. But another point to watch out for is that
these patches should be placed with adequate spacing from each other.
Otherwise, at high enough frequency, the wave energy will couple from one
patch onto the next patch and propagate down the board. This defeats the
purpose of keeping the patches small. What I would do is to space the
patches (or dots) with 4 times the dielectric height. If the top layer
dielectric is 5 mils thick, then the patch spacing should be 20 mils apart.
This ensures that the patches are better coupled to the plane layer below
than to the adjacent patch.
3. I would not recommend adding vias to tie these patches/dots to ground.
If you have a board running at 3Gbps, one tenth of the wavelength of the 5th
harmonic is about 80 mils in FR4. I would make the patches in the size
between 60 to 80 mils diameter. This would require the fab house to place
hundreds or thousands of patches. Adding that many vias to a board not only
increases the cost of the board but also increases the chance of power
planes shorting out if a via is drilled off center and the power plane
antipad is not large enough. In some cases, the short does not occur
immediately. But due to small cracks in FR4 and moisture content in the
material as electrolyte, copper atoms can migrate through the crack to cause
shorts later on. This is simply not a good idea.
4. Some mentioned about using the copper fill as a shield for
electromagnetic waves. This will work only if the fill is designed as a
faraday cage with vias closely stitched and no part of the circuit
penetrates the cage unless careful filtering is done on the circuits that
penetrate the cage. Otherwise, it will not work.
5. Some also mentioned that the copper fill can be used to terminate
electromagnetic waves to reduce emi emission. This idea rarely works. We
know that a signal on a transmissionline can be terminated by a matched
impedance load. A copper fill with vias tied to ground has an impedance
varying with frequency. This is a resonating structure at best. EMI
emissions from digital circuits occur at multiple frequencies, and these
frequencies can drift with temperature and / or change due to manufacturing
tolerances of discrete components (capacitors). Using a resonating
structure for impedance matching at multiple frequencies that may drift with
temperature is a task that few have even attempted. And even fewer have
succeeded.
6. Another person suggested using the copper fill to add parasitic
capacitance to lower the impedance of the board. This can work only if this
fill is placed near the circuit of interest. At low frequency, the whole
board behaves as a capacitor. This copper fill may help, but so do discrete
capacitors. At high frequency, the board behaves as a resonating structure,
adding capacitance a quarter wavelength away only creates more reflections
and/or shifts the resonance frequency of another circuit. Adding copper
fill randomly can create problems in some cases.
George
George Tang
LSI Logic
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