[SI-LIST] Re: Copper Fill

  • From: Alex McPheeters <amcpheeters@xxxxxxxx>
  • To: jeff.w.loyer@xxxxxxxxx,"'RayCaliendo@xxxxxxxxxx'" <RayCaliendo@xxxxxxxxxx>,si-list@xxxxxxxxxxxxx
  • Date: Fri, 14 Jun 2002 11:04:23 -0400

Actually,  we would consider anything above a speed, say 100mhz "exotic" enough
to warrant this concern and your note is well taken.  We specifically disallow
fabs working on our boards from any modification of data without our or the
client engineers approval.  In some instances, we may actually design thieving
in to prevent a fab from needing to do it, much the way we will spec milling or
panelization.

Great examples are fabs who apply thieving without checking (RE your concerns),
fabs who shrink or expand based upon material requirments without checking (any
dense board with areas of 4/4 space/trace could be blown by adjusting for
materials without considering this during design) and fabs who recalculate for
controlled impedance without checking with the engineer or designer. 

Though this is far off the original topic, we all should know and your
selection of bare-board vendor should also know that they should never "assume"
anything, today's PCB's tolerate very little assuming...


At 07:15 AM 6/14/02 -0700, Loyer, Jeff W wrote:
>
>This only applies to more exotic, expensive boards, but...
>
>If you have buried microstrip, don't let the vendor put the copper
>"thieving" over traces on that buried microstrip layer.  It will have
>substantial impact on those traces.
>
>I.E., in the drawing below, don't let the vendor put thieving on L1 where it
>is above traces on L2.  This also applies to lettering done with copper.
>
>L1: microstrip layer                  ---
>dielectric
>L2: buried microstrip                 ---
>dielectric
>L3: reference plane    -----------------------------------
>
>Also,
>I was surprised to hear it suggested to put a via (or more) in every fill
>square.  I've never heard of doing that, and it sounds prohibitively
>expensive.  But perhaps there's some VERY high frequencies at which it
>becomes necessary?  This is an area where I'm skeptical, and would have to
>see some demonstration of a board with and without vias on every fill square
>before I took is as Standard Operating Procedure.  Before I did that, I
>think I would abandon the fill altogether and find another way to deal with
>the issues that copper thieving addresses (board warpage, etching
>consistency, environmental concerns, are there more?).  But, just because I
>haven't had to do it yet, doesn't mean I won't be doing it in the future.  I
>never dreamed I'd be telling my vendor to not put copper over my buried
>microstrip traces...
>
>Jeff Loyer
>
>-----Original Message-----
>From: RayCaliendo@xxxxxxxxxx [mailto:RayCaliendo@xxxxxxxxxx]
>Sent: Thursday, June 13, 2002 3:20 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Copper Fill
>
>
>
>
>               Greetings,
>
>       Does anyone know, from theory or experience, what are the affects on
>               signal integrity or EMI, of putting copper fill in the open
>areas of the PCB
>               top and/or bottom?
>
>
>       Regards,
>
>       Ray Caliendo
>       EMC
>       Solectron
>
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Alex McPheeters
Vice President, Business Development
American Computer Development Inc.
Office - (301) 620-0900
Fax - (301) 620-9099
Cell - (301) 305-3051 

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