[SI-LIST] Re: Copper Fill
- From: Ritchey Lee <leeritchey@xxxxxxxxxxxxx>
- To: scott@xxxxxxxxxxxxx
- Date: Thu, 13 Jun 2002 17:22:19 -0700
Plane fills do not cause EMI problems. They don't need to be connected to
ground any more often that the component power pins make such connections. If
the fill is ground just to fill unused space with ground, that isn't of any
particular use. If the fill is to supplement the plane capacitance, the
connections to the appropriate power rail need only be made wher component pins
make connections.
As to how far to keep fill away from traces, the effect of too close a fill is
lowering the impedance of that trace. It is realtively easy to use a 2D field
solver to establish an adequate clearance. You will find that for a height of 5
mils, a spacing of 16 mils results in an imedance change of less than 1%.
Hope this helps.
Lee
Scott McMorrow wrote:
> Ray,
>
> When the separation of the copper fill from any signal is > 20 times the
> signal-to-plane spacing there is no effect on the signals. So, for 5 mil
> dielectric thickness, the fill area to signal trace clearance should be
> 100 mils or greater. I would also suggest grounding each fill area at
> multiple points to eliminate possible EMI coupling problems.. At a
> minimum, use ground stitch vias at four corners to contain resonances of
> the fill area. For extremely high speed multi-gigahertz systems, the
> vias should be spaced a maximum distance apart of 1/(f * Vp) apart.
> Where f = the upper frequency of operation and Vp is the velocity of
> propagation of signals within the dielectric.
>
> For FR4 Vp is around 180ps/in. For 3.125 Gbps signallling the upper
> frequency you are concerned with is the 3rd harmonic of the switching
> frequency, 4.68 GHz. In this case, the maximum stitch via spacing would be
> 1/(4.68e9 * 180e-12) = 1.18 inches.
>
> Best regards,
>
> Scott
>
> --
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 239-5536
> http://www.teraspeed.com
>
> RayCaliendo@xxxxxxxxxx wrote:
>
> > Greetings,
> >
> > Does anyone know, from theory or experience, what are the affects on
> > signal integrity or EMI, of putting copper fill in the open
> >areas of the PCB
> > top and/or bottom?
> >
> >
> > Regards,
> >
> > Ray Caliendo
> > EMC
> > Solectron
> >
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