[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR
- From: James_R_Jones@xxxxxxxx
- To: JackWCLin@xxxxxxxxxxxx, brian.p.moran@xxxxxxxxx,rsefton@xxxxxxxxxxxxx
- Date: Fri, 18 Oct 2002 09:56:53 -0500
All,
My understanding is that data is latched in by the strobes through a set of
registers. Obviously, the data has a relationship to the strobe (setup,
hold) in order to make this happen. I believe that there are two sets of
these registers in parallel, one that is positive strobe edge triggered, and
one that is negative strobe edge triggered. This is how data is latched
into the chip.
Now the data must be piped into the rest of the component, that is running
synchronous to the host clock. For this, a secondary row of registers is
used that is clocked by the host clock.
Now obviously, there is a relationship of host clock to strobe, or else the
data will not latch properly from the first two parallel registers (strobe
triggered) to the second set of registers (clock triggered).
I have used the datasheet data from the JEDEC spec for the DRAM
requirements, and the memory controller specification and derived timing
equations for this in the past. You won't ever know exactly what the delay
is in the part, but you can solve the equations based on what is given in
the two sets of timings. If you wanted to, you could solve the Strobe to
Clock relations simultaneously with the Data to Strobe relations in order to
find the Data to Clock relationships. Or you could just verify each
individually, my personal preference.
Hope this helps,
James R. Jones
Dell
-----Original Message-----
From: Jack W.C. Lin [mailto:JackWCLin@xxxxxxxxxxxx]
Sent: Thursday, October 17, 2002 9:53 PM
To: 'brian.p.moran@xxxxxxxxx'; 'rsefton@xxxxxxxxxxxxx'
Cc: si-list@xxxxxxxxxxxxx; Charles Lin; Tom B.C. Lin
Subject: [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR
Hi Brian:
Thanks for your reply, I have known that DQS did have relation with CK/CK#.
But I want to know is how to link their relation? Data latched for internal
DRAM cell should references to clock. My thought is:
Total DQ delay time (PCB flight+buffer delay) should be larger than Total
CK/CK# delay such that derive the constraint equation (this will get the
lower bound for DQ; and upper bound may derive from SI requirement). Is
that right? From board maker point of view, we don't know how much buffer
delay in the DRAM cell, if we know it's range, we can have more flexibility
in the design. Can you explain much more not only " In the case of the data
bus there = is an indirect timing relationship with CK/CK# by way of the
strobes." Thanks!
Jack
-----Original Message-----
From: Moran, Brian P [mailto:brian.p.moran@xxxxxxxxx]
Sent: Friday, October 18, 2002 9:27 AM
To: 'rsefton@xxxxxxxxxxxxx'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR
Robert,
I'm one of those guys at Intel that comes up with these rules based on
extensive simulations and verified in post silicon validation. You should be
= aware that while DDR is source synchronous as you say, all signals on the
DDR interface also have a timing relationship with CK/CK#. In the case of
control, = command, address, and strobes, this relationship is direct. In
the case of the data bus there = is an indirect timing relationship with
CK/CK# by way of the strobes. So every signal in the interface has a timing
relationship back to CK/CK# = and therefore their length must be defined and
controlled with respect to CK/CK#.=20
The 90 degree skew between DQ and DQS allows the DQs to be centered in = the
DQS sampling window when routed to equal lengths across a byte lane on the
MB. Some designs also have mechanisms to provide skew between other signal
groups and CK/CK# = such that they are centered in the CK/CK# sampling
window when routed with the natural routing flow of a typical multi-DIMM
placement. This is intended to eliminate the need = for extensive serpentine
on control signals and command/address busses. =20
Bottom line is you still have to create length matching rules for every
signal group with repect to clock.=20
=20
Brian P. Moran
Signal Integrity Engineer
Intel Corporation
brian.p.moran@xxxxxxxxx
-----Original Message-----
From: Robert Sefton [mailto:rsefton@xxxxxxxxxxxxx]
Sent: Thursday, October 17, 2002 2:33 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR
Jack -
The DDR controller vendors (e.g., Intel and AMD) are probably = compensating
at the board level for their CK/CK# output timing relative to DQ/DQS. = The
DIMM has setup and hold requirements for DQS relative to the falling = edge
of CK (about 200ps each). If this relationship doesn't exist at the =
controller output then it must be created at the board level by controlling
trace lengths.
Robert
----- Original Message -----
From: "Jack W.C. Lin" <JackWCLin@xxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, October 17, 2002 1:31 AM
Subject: [SI-LIST] Constraints on DQ/DQS and CK/CK# in DDR
> Hi All SI friends:
> I met a question about DDR. We all know that DDR is a source =
synchronus
> structure, data transfer will not depend on bus clock any more. In =
chip
> design, there exist Delay mechanism for DQ and DQS (90 degree phase =
shift)
> which is controlled by bus clock. But we found that either in Intel =
845
chip
> series or AMD K8 =A1K., they all have some layout constraint on =
DQ/DQS and
> command clock (CK&CK#). For example in Intel, if DQ/DQS length is Y,
CK/CK#
> is X, then they should follow X-4.4<=3DY. In AMD, Y=3DX+0.5 or =
Y=3DX-0.5. Why?
In
> DDR mechanism, it seems no reason to put such constraints on them. =
Maybe I
> miss something, is there anyone could provide a reasonable =
explanation?
> Thanks
>
> Jack
>
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