[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: "'rsefton@xxxxxxxxxxxxx'" <rsefton@xxxxxxxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Thu, 17 Oct 2002 18:27:13 -0700
Robert,
I'm one of those guys at Intel that comes up with these rules based on
extensive
simulations and verified in post silicon validation. You should be =
aware
that while DDR is source synchronous as you say, all signals on the DDR
interface also
have a timing relationship with CK/CK#. In the case of control, =
command,
address, and
strobes, this relationship is direct. In the case of the data bus there =
is
an indirect
timing relationship with CK/CK# by way of the strobes. So
every signal in the interface has a timing relationship back to CK/CK# =
and
therefore
their length must be defined and controlled with respect to CK/CK#.=20
The 90 degree skew between DQ and DQS allows the DQs to be centered in =
the
DQS sampling
window when routed to equal lengths across a byte lane on the MB. Some
designs also
have mechanisms to provide skew between other signal groups and CK/CK# =
such
that they
are centered in the CK/CK# sampling window when routed with the natural
routing flow of
a typical multi-DIMM placement. This is intended to eliminate the need =
for
extensive
serpentine on control signals and command/address busses. =20
Bottom line is you still have to create length matching rules for every
signal group
with repect to clock.=20
=20
Brian P. Moran
Signal Integrity Engineer
Intel Corporation
brian.p.moran@xxxxxxxxx
-----Original Message-----
From: Robert Sefton [mailto:rsefton@xxxxxxxxxxxxx]
Sent: Thursday, October 17, 2002 2:33 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR
Jack -
The DDR controller vendors (e.g., Intel and AMD) are probably =
compensating
at the board level for their CK/CK# output timing relative to DQ/DQS. =
The
DIMM has setup and hold requirements for DQS relative to the falling =
edge of
CK (about 200ps each). If this relationship doesn't exist at the =
controller
output then it must be created at the board level by controlling trace
lengths.
Robert
----- Original Message -----
From: "Jack W.C. Lin" <JackWCLin@xxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, October 17, 2002 1:31 AM
Subject: [SI-LIST] Constraints on DQ/DQS and CK/CK# in DDR
> Hi All SI friends:
> I met a question about DDR. We all know that DDR is a source =
synchronus
> structure, data transfer will not depend on bus clock any more. In =
chip
> design, there exist Delay mechanism for DQ and DQS (90 degree phase =
shift)
> which is controlled by bus clock. But we found that either in Intel =
845
chip
> series or AMD K8 =A1K., they all have some layout constraint on =
DQ/DQS and
> command clock (CK&CK#). For example in Intel, if DQ/DQS length is Y,
CK/CK#
> is X, then they should follow X-4.4<=3DY. In AMD, Y=3DX+0.5 or =
Y=3DX-0.5. Why?
In
> DDR mechanism, it seems no reason to put such constraints on them. =
Maybe I
> miss something, is there anyone could provide a reasonable =
explanation?
> Thanks
>
> Jack
>
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