[SI-LIST] Constraints on DQ/DQS and CK/CK# in DDR
- From: "Jack W.C. Lin" <JackWCLin@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 17 Oct 2002 16:31:31 +0800
Hi All SI friends:
I met a question about DDR. We all know that DDR is a source synchronus
structure, data transfer will not depend on bus clock any more. In chip
design, there exist Delay mechanism for DQ and DQS (90 degree phase shift)
which is controlled by bus clock. But we found that either in Intel 845 chip
series or AMD K8 ¡K., they all have some layout constraint on DQ/DQS and
command clock (CK&CK#). For example in Intel, if DQ/DQS length is Y, CK/CK#
is X, then they should follow X-4.4<=Y. In AMD, Y=X+0.5 or Y=X-0.5. Why? In
DDR mechanism, it seems no reason to put such constraints on them. Maybe I
miss something, is there anyone could provide a reasonable explanation?
Thanks
Jack
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
