[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR
- From: Vinu Arumugham <vinu@xxxxxxxxx>
- To: JackWCLin@xxxxxxxxxxxx
- Date: Thu, 17 Oct 2002 10:30:35 -0700
DDR SDRAMs have an input timing requirement between DQS and CK/CK#. The length
constraint may be related to that.
Thanks,
Vinu
"Jack W.C. Lin" wrote:
> Hi All SI friends:
> I met a question about DDR. We all know that DDR is a source synchronus
> structure, data transfer will not depend on bus clock any more. In chip
> design, there exist Delay mechanism for DQ and DQS (90 degree phase shift)
> which is controlled by bus clock. But we found that either in Intel 845 chip
> series or AMD K8 ¡K., they all have some layout constraint on DQ/DQS and
> command clock (CK&CK#). For example in Intel, if DQ/DQS length is Y, CK/CK#
> is X, then they should follow X-4.4<=Y. In AMD, Y=X+0.5 or Y=X-0.5. Why? In
> DDR mechanism, it seems no reason to put such constraints on them. Maybe I
> miss something, is there anyone could provide a reasonable explanation?
> Thanks
>
> Jack
>
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