[SI-LIST] Re: Antwort: Re: Questions about interplane capacitance
- From: "Chris Cheng" <Chris.Cheng@xxxxxxxx>
- To: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- Date: Sat, 15 Mar 2008 22:34:21 -0700
I think they are called PCIe I II III and FBDIMM. Or whatever RAMBUS called
their latest .....
In any case, before we say the sky is falling, let's put things in perspective
and consider your average memory controller, FSB IC package I/O power delivery.
What is the typical signal to power/ground pin ratio ? What is the loop
inductance of those package power/ground pins and die to package redistribution
(or God forbid a wire bond) to signal multiplied by the signal to ground/power
ratio ? How do those highly perforated package planes compared with your 80mohm
PCB planes ? How does your average DIMM socket power/ground inductance looks
like ? Or inductance of those cheap BGA package on DDRXX device ? If the signal
edge can even be generated from your package I/O power delivery and goes
through the package, chances are it will make it through your PCB reference
plane PROVIDED you have at least a good reference ground plane with proper
return vias and I/O pad return capacitance.
As usual, I am just a dumb lazy engineer who don't like to pay and do
unnecessary things when I think the limitation is in other places.
________________________________
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
Sent: Sat 3/15/2008 8:10 AM
To: Chris Cheng
Cc: istvan novak; steve weir; Joel Brown; SILR; Istvan Novak;
si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Antwort: Re: Questions about interplane capacitance
Chris
Now tell the memory, processor and chipset vendors that and get their buy-in to
switch from Single Ended to Differential data lines.
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com <http://www.teraspeed.com/>
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Chris Cheng wrote:
There is a very cost effective way to eliminate signal induced plane
resonance.
It is call differential signal. Differential mode is orders of
magnitude smaller vs. common mode noise injection into planes.
________________________________
From: istvan novak [mailto:Istvan.Novak@xxxxxxx]
Sent: Fri 3/14/2008 7:31 PM
To: Chris Cheng
Cc: steve weir; Joel Brown; SILR; Istvan Novak; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Antwort: Re: Questions about interplane
capacitance
Chris,
This seems to be one of those topics, which are governed by beliefs and
it is hard to convince each other.
The important thing is that people understand the physics behind the
circuit and the way how various options can be used to solve the task.
From that point on it is the designer's responsibility to weigh the
constraints and the options and to come up with a working design.
Regarding plane resonances, you are correct in saying that if you do not
excite them, they make no harm. However, if there is a cost-effective
way to eliminate them, I rather choose to eliminate the resonances
rather than worrying that they dont get excited.
Regards,
Istvan
Chris Cheng wrote:
Ok, now we eliminate the claim that core power distribution
needs fancy PCB planes and decoupling solutions at the PCB level.
As you say if the core plane is used as reference planes, what
controls your plane capacitance/loop inductance ? The impedance control for the
stripline that they sandwich or your fancy power plane scheme ?
This whole plane resonance also borders me. A few months ago we
have already have long discussion here about a CAD tool vendor and another
company's paper claiming plane resonances in simulation and measurement. As I
have pointed out then and I will repeat again now, that was just a matter of
via placement for signal return rather than real plane resonance. Both the
measure and simulation conditions were set at an unrealistic condition to scare
people into thinking there is a plane resonance problem. I have always maintain
signal return issue on PCB is a matter of proper reference plane and return via
placement, NOT fancy decoupling. If you shoot yourself in the foot and then run
around claiming you need a fancy stretcher, I really have nothing more to add.
-----Original Message-----
From: Istvan.Novak@xxxxxxx [mailto:Istvan.Novak@xxxxxxx]
Sent: Friday, March 14, 2008 6:31 PM
To: Chris Cheng
Cc: steve weir; Joel Brown; SILR; Istvan Novak;
si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Antwort: Re: Questions about
interplane
capacitance
Chris,
You are right; if we speak about a single point-of-load CPU
core power
distribution, we *may* not need to worry about high-frequency
behavior
on the board. However, as always, it depends. IF your power
rail feeds
only the particular CPU core, AND you do not use those planes
as signal
reference, AND if you do not need to go through this plane
cavity with
vias of sensitive signals, all you need is a low-frequency
design,
because the connecting inductance between the board and die
filters out
the high-frequency noise. However, when signal quality may be
impacted
by the plane resonances (for instance because the core plane is
also
used as a return plane), it is a good idea to make a design
that creates
a decent impedance profile up to the relevant bandwidth of the
signal.
Regards,
Istvan
Chris Cheng wrote:
Steve,
What if the package of any IC act as a low pass filter
that has a cut off at 100MHz or lower that seperate the fancy 80mohm PDN and
the actual IC load ? What can all those highspeed caps and the transmission
line planes do to help the IC ? At 100MHz or below, do I still need to worry
about transmission line mode or just place the caps and regulator close enough
and use a lump model ?
If I look at the power decoupling requirements of the
latest highspped CPU's, I am not sure if they even border to ask for 100MHz or
above decoupling caps on the PCB other than for filters ?
May be above 100MHz core power decoupling at system PCB
level is not neccessary ?
I certainly have done a few that suggest so.
Chris
_____
From: si-list-bounce@xxxxxxxxxxxxx on behalf of steve
weir
Sent: Fri 3/14/2008 12:24 AM
To: Joel Brown
Cc: 'SILR'; 'Istvan Novak'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Antwort: Re: Questions about
interplane capacitance
Joel, a driver pumping into an infinitely long, or
ideally terminated
transmission line never sees a far end because no
energy ever reflects
back. A PDN that is arranged to look like an ideal
infinite
transmission structure, similarly reflects nothing back
to the load.
All the load sees is the characteristic resistive Z of
the transmission
structure it is attached to.
Best Regards,
Steve.
Joel Brown wrote:
I hate to prolong this but...
When I think about a transmission line in the
normal sense (signal
propagation), A driver switches at one end but
initially all it sees is
Zo
which looks like a resistor maybe 50 ohms and
it does not even see the
load
until wave propagates the length of the line.
So there is a time delay..
Now
think of the driver being the power pin of the
IC and the load being the
bypass cap on the corner of the board or visa
versa and I see a
propagation
delay, so what am I missing?
Joel
-----Original Message-----
From: SILR [ mailto:silr@xxxxxxxxxxxx]
Sent: Thursday, March 13, 2008 6:27 PM
To: 'steve weir'; 'Joel Brown'
Cc: 'Istvan Novak'; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Antwort: Re:
Questions about interplane
capacitance
Joel asked:
<<< ...why is charge propagation velocity not a
factor when the PDN is
purely resistive? >>>
Well, here's a crazy way to think about this
(which I'm sure not
everyone
will agree)... I guess this would be like how
Eric B. might put it...
"Be
the Signal"
I'm the charge on some corner of a
board...there's an IC in the middle
of
the board...
I have to get to that IC using this
transmission line called the PDN.
If
this Transmission Line had the classical Ls and
Cs (and Rs) to describe
its
characteristics, then that means I have to deal
with changing EM fields
to
get to that IC... but these time varying EM
fields always cause some
delay
in my charge getting to that IC in a timely
manner...
BUT!!! ...if this Transmission Line had nothing
but Rs (no Ls and Cs) to
describe its characteristics then that means I
don't have to deal with
time
varying EM fields any longer... I just have
to deal with resistive
losses
only but this only equates to a drop in Static
Voltage Potential and
nothing
more... (so keep the Z low!!!) And I can get
there (to the IC) in no
time
and the IC gets the charges that it needs and
it wouldn't even know
anything
is different...
Again, this is a crazy way to look at this...
but it works for me, for
now... until I get grilled by the senior
members... :-)
Silvester
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [
mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of steve weir
Sent: Thursday, March 13, 2008 5:57 PM
To: Joel Brown
Cc: 'Istvan Novak'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Antwort: Re: Questions
about interplane
capacitance
Joel, it is transmission line theory. Think
about an infinitely long
signal transmission line for a moment. At any
instant a driver sees a
constant impedance across frequency. The
voltage to current relation is
independent of prior history. What Istvan
describes is a very low
impedance
transmission structure for power.
Sadly, a lot of IC vendors are still playing
catch-up in terms of power
delivery. If they had their game together,
they would be telling you:
The actual voltage tolerances at the die, the
current spectrum at the
die,
and the parasitics of the die and package.
From that you could engineer
your PDN. Instead often what we see are
partial recipes like you
describe.
On a good day the recipes cost extra money. On
a bad day, they result
in
failures.
One can build a resistive networks several
ways. One is to add discrete
resistance by any number of methods, another is
to use the FDTIM method
that
Larry Smith has long championed. And even
though resistive networks
have
attractive qualities, reactive networks may
still be cheaper and equally
effective. It all depends on the
circumstances. It is somewhat akin to
surface finishes: there is no ideal one. But
there are several that
when
used properly work very well. One just needs
to respect the limitations
of
each method.
Part of the problem figuring this stuff out is
having sufficient
experience
to judge trade-offs early in the design
process. That's just something
that
has to be learned. As more training materials
come out on power
delivery,
it will probably get easier. In the shameless
plug department, we (
Teraspeed ) do very nice jobs optimizing power
delivery systems for
customers. If you've got a design you want
advice on we can get you
squared-up pretty quickly.
Best Regards,
Steve.
Joel Brown wrote:
Steve,
So even though each cap has a
relatively high ESR (1.6 Ohms) the PDN
as a whole has a relatively low
impedance which will result in low
noise on the PDN. This goes against
intuition and previous thinking
that an IC needs a local bypass with
low ESR and ESL to supply the
needed charge during switching
transients. I am starting to see that
mathematically a resistive PDN lowers
noise compared to one that is
the inductive (you did a good job
explaining that). The thing that I
am having trouble grasping or
visualizing
is that why is charge propagation
velocity not a factor when the PDN
is purely resistive? Is the PDN model
simply a resistor in series with
the
load
and distance has no effect? Perhaps
there is an analogy that would
make
this
concept easier to understand? Also,
when I see app notes from IC
vendors that recommend using a 0.1uF
and 1000pF cap on each supply pin
and then instead I use distributed high
ESR capacitors I feel like I
am doing something quite different and
contrary from the recommended
and when I
query
the vendors on how they arrived at
recommendations in the app note the
answer I get is "we recommend that you
do it exactly as shown in the
app note, we know it works that way and
if you don't follow it it may
not
work".
Also I am wondering how all this
relates to X2Y caps, I suppose they
could be used with series resistors but
that would somewhat defeat the
purpose
by
adding inductance. Its not clear to me
what approaches I should
attempt on future designs.
Joel
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[ mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of steve weir
Sent: Wednesday, March 12, 2008 11:26 PM
To: Doug Brooks
Cc: Istvan Novak; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Antwort: Re:
Questions about interplane
capacitance
Doug, Istvan's representations are
analytically exact. When the
characteristic impedance of the
transmission structure is high, and/or
the rise times are slow then capacitors
can be placed in close enough
proximity
that they load the transmission
structure so as to make it appear a
lower impedance with some little bumps.
For example if one had a 10"
x 10" 4
mil
er4.0 board = 22.5nF and loaded it with
bypass every square inch of
150pH, then for slow enough signals,
the distributed impedance would
look like 80mOhms. If the network were
constructed from 200
capacitors, an ESR
value
of 1.6Ohms / cap would make that
impedance uniform down to the RC knee
of the parts. Assume that were matched
by an AVP regulator of 80mOhms
and
the
entire thing looks like 80mOhms from DC
to over 1GHz. 80mOhms would
support
a 32 bit transition w/ about 5% droop.
The impedance scales with
dielectric
height and the inverse square root of
eR. Scale the dielectric down
to 0.1mils and now 320 lines can switch
simultaneously in one
direction with
5%
droop, and at arbitrary edge rates.
Istvan has shown using analysis with
the reverse pulse technique an
inductive PDN shunt impedance acts like
a noise high pass filter (
See DC papers from at least as far back
as DC East 2005 ). Put in a
square wave noise pulse ( load current
) and the leading edge changes
by Vdelta = -L*di/dt below the
baseline. Allow the pulse to persist
long enough and
the
system recovers back to the baseline
which would be -I*Rpdn.
Return the load current to zero, and
now the energy stored in the
inductance
kicks back -L*di/dt. The p-p noise is
then 2*Ldi/dt -
(Imax-Imin)*Rpdn.
If
Rpdn is very small then it approximates
2*Ldi/dt.
This behavior is apparent in the
transient response plots of virtually
any non-AVP VRM.
Now, suppose that the VRM and PDN can
be made to appear resistive
right through Fknee. Then the response
to a current pulse of I is
simply Vdelta
=
-I*Rpdn. There is no component of
di/dt, and so the total p-p noise
is
just
(Imax - Imin)*Rpdn. AVP schemes
position the DC operating point
intentionally high so that at Imin they
are at their margined high
limits and at Imax they are at their
low limits. This allows
increasing Rpdn
while
still meeting the same current and
voltage specifications.
Best Regards,
Steve.
Doug Brooks wrote:
Istvan,
With all due respect, I would modify
your argument a little bit. In
very simplistic terms, suppose we need
x amount of charge to
transition from a zero to a one in one
ns. That amount of charge (I
suggest) must be within
6 inches of the need (what I think we
are referring to as the service
radius). If not, it takes a little
longer to reach the logical one
state.
I look at it, not from the standpoint
of a dip in the rail, as much
as the ability to satisfy the rise time
requirement (unless you are
referring to a dip in the rail that
occurs during the rise time
itself.) In the slightly longer term,
the charge will replenish
fairly quickly, but not, perhaps fast
enough to meet the rise time
requirement.
Doug Brooks
Andreas,
Yes and no. It is true that charge
moves with finite speed, so for
any given time duration the charge has
to come from locations closer
than the ratio of distance over speed.
BUT the whole notion of
service radius is based on the
assumption that as you deplete the
charge available in the immediate
vicinity of the active device, you
have to wait for replenishment,
otherwise you get a big dip on the
supply rail.
Having a matched
transmission medium to deliver power to
the active device, the
charge moves without interruption, and
as you deplete the planes
close to the device, it gets
replenished on the fly from areas
further away, so the service area
concept is pretty much meaningless
in this scenario. Current flows
without interruption.
The bucket brigade of infinitesimally
small inductive and capacitive
elements of the transmission line
transmits the power continuously.
If the load current changes, for any
I(t) time function of load
current, the transient noise at the
load point will be I(t)*Zo,
where we assume that Zo is the
resistive and frequency independent
characteristic impedance of the
transmission medium. This is a very
simplistic one-dimensional model, but
it gives a good insight of why
the service radius matters only on PDNs
where the network is not
matched.
Regards,
Istvan Novak
SUN Microsystems
Andreas.Lenkisch@xxxxxxxxxx wrote:
Istvan,
I'm wodering a little about your
comments to the service radius.
Independant if the impedance is
resistive, we have still a
propagation time which would limit the
service radius from my
understanding.
Do I'm wrong?
regards
Andreas
Istvan Novak <istvan.novak@xxxxxxxxxxx>
<mailto:istvan.novak@xxxxxxxxxxx> Gesendet von:
si-list-bounce@xxxxxxxxxxxxx
11.03.2008 13:14
An
Joel Brown <joel@xxxxxxxxxx>
<mailto:joel@xxxxxxxxxx>
Kopie
si-list@xxxxxxxxxxxxx
Thema
[SI-LIST] Re: Questions about
interplane capacitance
Joel,
Just one quick comments to the good
summary from Steve:
While considering planes and bypass
capacitors in terms of
effective capacitances and inductances
is a valid approach, we need
to keep in mind that focusing on the
capacitive or inductive nature
of parts without looking at the wider
picture misses a very
important and useful class of
solutions, namely that of matched
transmission lines. As it was pointed
out earlier several times on
the SI list, the best
(self) impedance for a power
distribution network is a resistive
one, neither capacitive, nor inductive.
We can get resistive impedance from a
matched transmission line,
regardless of its capacitance and
inductance, and in such cases the
notion of 'service area' of parts
become meaningless: you can put
bypass components further away from the
active devices without
sacrificing performance.
Regards,
Istvan Novak
SUN Microsystems
Joel Brown wrote:
Interplane capacitance is frequently
cited as the only effective
bypass capacitance on a PCB at
frequencies above 200 MHz.
I am currently working on a design
which brings up some questions
regarding
interplane capacitance.
1. Power planes normally carry
"standard" voltage rails that are
used throughout a board such as +5V and
+3.3V.
High speed ICs usually have core
voltages that are local to the IC
and
are
provided by a local regulator which
converts the standard rail to
the
core
voltage (example 3.3 to 1.8V).
The local core voltage is distributed
on a plane area that is
local to
the
IC and therefore is small in area (0.25
sq in or less) which
results in
a
very small amount of interplane
capacitance.
Is this very small amount of
capicitance effective for bypassing
the IC?
I
am sure it depends somewhat on the
current waveform being drawn by
the
IC
but this can only be estimated because
semiconductor manufacturers
do
not
provide current consumption profile as
a function of frequency. To
make matters worse, some ICs have
several different VCC pins which
the manufacturer recommends connecting
to separate networks of
bypass caps
and
ferrite beads. This cuts the power
distributuion up even more
resulting
in
less (practically zero) interplane
capacitance. It is somewhat
ironic
that
the the voltages such as +5V and +3.3V
which are required at
points
across
the whole board and therefore have the
most interplane capacitance
are
also
the voltages which have least
requirement for interplane
capacitance
because
they do not directly supply high speed
rails.
2. There has been a lot of emphasis on
reducing the mounted
inductance
of
bypass capacitors. Even with this
reduced inductance they are
still only effective up to several
hundereds of MHz at which point
the interplane capacitance becomes the
only bypass capacitance
mechanism. However there
is
inductance between the connection of
the IC to the planes. This
inductance
consists of vias and package
inductance. I did look for some
numbers for package inductance and did
not find much, it seems to
be a closely held secret. Also it is
unknown how much bypass
capacitnace is internal to
the IC
package. Just for example if we assume
250pH for the vias and 500
pH for
the
package, then the impedance at 500 MHz
would be 2.36 Ohms. This
seems
rather
high for the interplane capacitance to
be of much benefit.
In summary how much interplane
capacitance is needed to be
beneficial,
and
why is it beneficial given the
inductance in the vias and package?
Thanks - Joel
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