I, also, have experienced this. It seems to happen generally where 2 vias are close enough that they create a sliver between them. I have found that instead of changing the rules, which I do not like to do, moving one of the vias a tiny bit resolves the problem. The peculiar thing is even with the same two vias the problem won't manifest itself on other plane layers. I put an SR in on this and I hope that Cadence can find and fix this annoying bug (or is it a feature?). One other thing, since the difference is significantly less than a mil, which will get lost in processing, you can safely ignore these DRCs if you wish.
Hope this helps a little, Kevin McCowan Sr. PCB Designer TSI Telsys
I have experienced the same thing - try adding a oversize value to the clearance and it will take care of the problem. I think it's a rounding error.
Set the clearance oversize to 1 mil or larger
Gerry Meier Sr. PCB Designer Freedom CAD Services, Inc. Voice: (603) 864-1300 x1350 Alt. Voice: (386) 753-0048 Email: gerry.meier@xxxxxxxxxxxxxx visit our website at<http://www.freedomcad.com
-----Original Message----- From: sjcharles@xxxxxxx [mailto:sjcharles@xxxxxxx] Sent: Thursday, June 10, 2004 9:27 PM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] gnd plane and drc errors
To all gurus: I have multiple gnds (pwr,signal,earth and shield) and i need to edit all layer, so i'll change all planes to dynamic shape and let program clear all via that don't need to be tied. But i always get drc errors, rule says 8 mils but the opening is 7.99 mils. What gives? after i'm finish i change shape type back to static and tie all the four types of gnds back together around board edge. Why do i always get the 7.99 mils? thanks in advance Sam
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