[PCB_FORUM] Re: ICU2004 - PCB Top 5 Issue's
- From: "Musetti, Carl" <cmusetti@xxxxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 24 Jun 2004 10:34:00 -0400
I would have rather seen it implemented like specctra where the can different
clearances stet for pin to pin spacing, rather than just having it not check it
all. But it is true that getting rid of the constraint areas for these type of
components with the fine pitch pins will be a performance boost.
-----Original Message-----
From: Schwartz, Jerome [mailto:jschwa01@xxxxxxxxxx]
Sent: Thursday, June 24, 2004 10:21 AM
To: 'icu-pcb-forum@xxxxxxxxxxxxx'
Subject: [PCB_FORUM] Re: ICU2004 - PCB Top 5 Issue's
Thanks Ed. The property NODRC_SYM_SAME_PIN was actually a PCR that I
submitted. It will drastically
reduce constraint areas on fine pitch components thereby boosting performance.
Regards,
Jerry Schwartz, CID+
IPC Certified Designer
"May The Schwartz Be With You."
Designer 3
Harris Corporation GCSD Voice (321)-727-5474
P.O. Box 37, MS 1/9843 Fax (321)-727-6007
Melbourne, FL 32902-0037 Pager (321)-690-9797
mailto:Jerome.Schwartz@xxxxxxxxxx
http://www.harris.com <http://www.harris.com/>
-----Original Message-----
From: Ed Hickey [mailto:ehickey@xxxxxxxxxxx]
Sent: Thursday, June 24, 2004 9:51 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: ICU2004 - PCB Top 5 Issue's
There will be a method to suppress certain DRCs in 15.2 by applying properties
to the objects.
DRC Suppression in 15.2 (June 28, 2004)
3 new properties are available to suppress typical 'false' type DRCs. In 15.0,
the property NODRC_SYM_SAME_PIN was introduced that suppresses pin to pin
spacing errors within the same component. Use of some of these properties may
alleviate the requirement for constraint areas or time spent reviewing each
instance of error.
* NODRC_COMPONENT_BOARD_OVERLAP - apply directly to component placebound
shape when components overlap the package keepin area. Typically these
components tend to be mechanically constrained like connectors, switches and
LEDs.
* NODRC_ETCH_OUTSIDE_KEEPIN - apply directly to etch elements outside the
route keepin area.
* NODRC_VIAS_OUTSIDE_KEEPIN - apply directly to vias placed outside the
route keepin area. These vias tend to be GND stitching vias in large
quantities. The use of temp groups is recommended when suppressing a large
quantity of vias.
-----Original Message-----
From: Musetti, Carl [mailto:cmusetti@xxxxxxxxxxxxxxxx]
Sent: Thursday, June 24, 2004 9:00 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: ICU2004 - PCB Top 5 Issue's
I completely agree with you Jerry Allegro DRC system is one of the strongest
features of the tool and to have it made so that errors are acceptable is
unacceptable!
-----Original Message-----
From: Schwartz, Jerome [mailto:jschwa01@xxxxxxxxxx]
Sent: Thursday, June 24, 2004 7:48 AM
To: 'icu-pcb-forum@xxxxxxxxxxxxx'
Subject: [PCB_FORUM] Re: ICU2004 - PCB Top 5 Issue's
For all of you that have been doing real design work for 25 years or more
please, please, please, do not let something like this
pass through to Cadence. An error is an error. There is no such thing as a
false DRC. The system is trying to tell
you that something is wrong. Understand the error, make it your friend, then
correct it. It will go away, no hard feelings.
I have never sent a design to be fabricated with DRC's. There's always a way to
correct the error. I've seen most of it, if not all.
No DRC at required areas:
False DRC errors should have some way of making the tool not report them as
errors.
Regards,
Radha Krishnan G.
Layout Design Engineer
Caliber InfoTech India P Ltd.
35/1, 10th Street, Gandhipuram,
Coimbatore-641012
Tamil Nadu
India
Phone:+91-422-5371411
caliber logo
<file:///C:/Documents%20and%20Settings/Administrator/My%20Documents/My%20Pictures/Caliber-Logo1.jpg>
-----Original Message-----
From: local [mailto:suresh@xxxxxxxxxxxx]
Sent: Tuesday, June 22, 2004 7:51 PM
To: felix@xxxxxxxxxxxx; grk
Subject: Fw: [PCB_FORUM] ICU2004 - PCB Top 5 Issue's
----- Original Message -----
From: sureshbabu <mailto:suresh@xxxxxxxxxxxxxxx>
To: felix@xxxxxxxxxxxx ; grk@xxxxxxxxxxxx
Sent: Tuesday, June 22, 2004 7:47 PM
Subject: [PCB_FORUM] ICU2004 - PCB Top 5 Issue's
Dear PCB Forum Member,
The International Cadence Users Group PCB SIG is now soliciting input for this
years PCB Top issues. Now is your chance to influence the functionality of the
Cadence PCB products. This year we are doing things a little differently than
previous years by having individual Top Five issue lists for the following
Allegro Platform products: Concept HDL, Capture/CIS, Allegro, APD,
SpecctraQuest/SigXP/CM and Specctra.
The schedule will be as follows:
Input Begins: June 22, 2004
Input Ends: July 19, 2004
Top-5 Voting Begins: July 26, 2004
Voting Ends: August 6, 2004
Results Published: TBD
Cadence's response to the Top-5 Issues will be shown as a presentation at the
2004 International Cadence Usergroup Conference and shortly there after the
responses will be posted at <http://www.cadenceusers.org/>
http://www.cadenceusers.org. Only the responses, and not the entire
presentation will be posted.
Please visit the following link to submit issues for this years Top 5 voting.
http://www.cadenceusers.org/sigs/pcb/pcbIssuesSubmit2004.html
In addition please checkout our website for Conference Updates, Schedule and
Registration Specials
We are looking forward to hear from you
ICU PCB SIG
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