[PCB_FORUM] Re: Bottom Side SMT Testpad Definition
- From: "Macindoe, Gary" <Gary.Macindoe@xxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Fri, 25 Jan 2008 09:54:14 -0600
Hey Dave,
Wow, I can't believe no one responded to this.
I typically don't have to worry about testprep (yes it's nice!), but
can't you just mirror the test via to the bottom?
I can't remember, it's been too long, but just mirroring it might work.
Anyway, creating a padstack to default to the bottom is really easy.
Define your bottom TP for the "END LAYER" and "SOLDERMASK_BOTTOM" only
(no paste!).
Here is an example of a padstack used for the bottom of an edge
connector:
In your TP symbol, define Bottom Assembly, Bottom ref des etc.
Good luck!
Gary E. MacIndoe
PCB Design Engineer
Fort Collins, Colorado
amd.com
gary.macindoe@xxxxxxxxxxxxxxxxxxxx Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Dave Schaefer
Sent: Thursday, January 24, 2008 2:43 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Bottom Side SMT Testpad Definition
I've defined a via for use as a testpoint "TP40SP" which is a .040"
square pad (smt / surface layer only). When I bring this via into a
design, it defaults to the Top side, and cannot be used as a Bottom Side
Tespoint in testprep.
How do I define a bottom side SMT (single layer) testpoint "via"
padstack?
Dave Schaefer
dave.schaefer@xxxxxxx
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