[PCB_FORUM] Bottom Side SMT Testpad Definition
- From: Dave Schaefer <dave.schaefer@xxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 24 Jan 2008 15:43:01 -0600
I've defined a via for use as a testpoint "TP40SP" which is a .040" square pad
(smt / surface layer only). When I bring this via into a design, it defaults to
the Top side, and cannot be used as a Bottom Side Tespoint in testprep.
How do I define a bottom side SMT (single layer) testpoint "via" padstack?
Dave Schaefer
dave.schaefer@xxxxxxx
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