[SI-LIST] Re: decoupling
- From: Ed Priest <Ed_Priest@xxxxxxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 11 Jul 2001 18:07:33 -0700
Caps do two things.
1. Noise prevention
a. They bypass the inductance to prevent Ldi/dt from forming in the
first place.(here they have to be on the right side of the inductance
b. They provide localized charge to prevent a voltage collapse due to
coulomb starvation.
2. Coupling - they provide a low impedance short between power and ground.
1. If the package is too inductive then the capacitance on the board will not
prevent the Ldi/dt noise from happening.(your point)
1B. If the time of flight between the current switch and the capacitor is too
far it will prevent the coulomb starvation from happening by the current switch
for x psecs(nsec?). That is why you try and keep the capacitors close and with
very little inductance in the path.(your point?)
2. Even if the noise happens it is a very good idea to have tight coupling (low
impedance) between the power and ground to lower the noise (di x Zo) and to
common what noise there is.
Doing as Larry suggests is a good thing.
For you comment that 400Mhz can not propagate through the package ( good
packages can propagate higher frequencies than that) - how to you think the Ghz
+ signals get out. The noise that comes out is a voltage divider between the
reactance on the die/package and the power distribution impedance on the board
- another way to see why you want the impedance on the board to be small.
Ed
-----Original Message-----
From: Chris Cheng [mailto:chris.cheng@xxxxxxxxxxxx]
Sent: Wednesday, July 11, 2001 4:11 PM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: decoupling
larry,
sorry if i sound like a broken record. i don't believe in
thin dielectric power plane function as a hi frequency noise
suppression in a real system. my thinking is based on
a) hi frequency core noise cannot propagation through the
package back to the pcb, not at 400MHz. same reason you
have sso limitation on a package, its just as bad to
go out of than go into a package.
b) i/o switching noise is related to the image current
return path which exist between the power plane sandwiching
the signal layers and dictated by the impedance control
of the stackup.
yes you get the hi frequency capacitor you described but
it is not effective in suppressing the above noise.
look at the complete picture of the source and destination
of the noise. not just an intermediate part.
chris
-----Original Message-----
From: Larry Smith [mailto:ldsmith@xxxxxxxxxxxxxxxxxx]
Sent: Wednesday, July 11, 2001 3:11 PM
To: si-list@xxxxxxxxxxxxx
Cc: ldsmith@xxxxxxxxxxxxxxxxxx
Subject: [SI-LIST] Re: decoupling
Khalid - Larry Miller has already provided an answer that I pretty much
agree with. Discrete decoupling capacitors are rapidly loosing their
effectiveness between 200 and 400 MHz because of their inductance. We
have been able to obtain a total mounted inductance (ESL) of about
500pH for discrete capacitors. With further improvements, we may be
able to drop that to 350pH. But at 400 MHz, that 350pH ESL is 879 mOhms!
Through the wonders of series resonance, we can use a 470pF NPO
capacitor with a (measured) 140 mOhm ESR to apply a 140 mOhm resistance
across the power planes at 392MHz, even though the impedance of the ESL
is 879mOhms. This particular capacitor has a Q of 6.3, so I would
classify it as a very low ESR capacitor. But it can be useful against
a 400 MHz EMI problem frequency if it is precisely located on the power
planes.
You have to have software tools to place capacitors of this frequency
in effective positions. Several such capacitors may bring the impedance
down below 50 mOhms, but things get really tricky at these frequencies
and impedances. Also, capacitors with a Q this high can cause
impedance peaks at slightly higher and lower frequencies. (This is
playing with fire and you can get burned...) We have been successful
at obtaining a measured 6 mOhms at 600MHz by using capacitors on power
planes, but I question whether that was really necessary to make a
successful product.
A far better solution is to use the impedance of closely spaced power
planes to decouple above several hundred MHz. Consider the following
table of FR4 (dK=4) power plane characteristics:
dielectric capacitance spreading impedance
thickness (pF/sq in) (pH/square) (mOhm-inch)
---------- ----------- ----------- ----------
4 mil 225 130 750
2 mil 450 65 325
1 mil 900 32 162
Even with 4 mils of separation between power planes, we get 225pF for
every square inch. Capacitance is inversely proportional to thickness
so we get much more capacitance as we cut the dielectric thickness in
half and then cut it in half again.
But even more important than that, the spreading inductance of the
power planes drops from 130 pH per square to 65 and then 32 pH per
square as the dielectric gets thinner. The spreading inductance alone
on 4 mil power planes is very comparable to the ESL of the best mounted
capacitors. There is no point in placing a bunch of low ESL capacitors
on a pair of power planes unless the spreading inductance of the
planes is well below the parallel inductance of the capacitors.
An even better figure of merit for the power planes is the impedance.
A one inch wide strip of 4 mil power plane material has 750 mOhms of
impedance. At high frequencies (frequency where the lateral distance
on a PCB is not negligible compared to the wavelength) the power plane
impedance becomes very important. There is no point in paralleling a
bunch of low ESR, low ESL capacitors together to hit a 10 mOhm target
impedance if the power plane impedance that connects the capacitors to
the power consumers (uP, ASICs) is higher than the capacitors. It's
like trying to supply the city's water through a garden hose.
The short answer to your question is that above several hundred MHz,
the power planes are not only sufficient for decoupling, but absolutely
necessary for it. There are several companies that are beginning to
provide power plane material that is 1 mil or thinner (i.e. Dupont and
3M). The trick is learning how to incorporate this material into PCBs
and electronic packages. I believe this is the key to low impedance
power distribution in the GHz range.
BTW, there is a paper out on the si web site that describes power plane
modeling and simulation results. An extension to this paper will be
published in the August 2001 IEEE Transactions on Advanced Packainging
that defines and discusses spreading inductance (if I can get the final
edits in on time...).
http://www.qsl.net/wb6tpu/si_documents/docs.html
There is also a paper that talks about a distributed model for discrete
capacitors. That paper contains some information on how to measure the
performance of capacitors mounted on power planes. It is temporarily
located at
http://groups.yahoo.com/group/si-list/files/Published%20SI%20Papers%20from%2
0Sun/
regards,
Larry Smith
Sun Microsystems
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