[SI-LIST] Re: decoupling
- From: "sweir" <weirsp@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 20 Jul 2001 11:16:13 -0700
Johnni,
Use a low inductance pad / via pattern for both capacitor pads to plane.
Place vias for the IC as close as your DFM rules allow. Place the capacitor
anywhere close to the part. The capacitor is supporting the planes, the
planes are supporting the part. Whatever you do, DO NOT extend traces out
from the capacitor pads, or the IC pads to the pwr/gnd vias any more than
your DFM rules require.
Regards,
Steve.
----- Original Message -----
From: <johnni.friis@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Friday, July 20, 2001 4:48 AM
Subject: [SI-LIST] Re: decoupling
>
>
> Hi,
>
> I'll have to bee more specifik, sorry.
> I got an IC in a So20, where should I place the cap, near the Vcc pin (pin
> 20) or near the GND pin (pin10) ?
> I would say near the GND pin, the current would travel the longest path in
> the Vcc plane,
> creating more noise in the Vcc plane and than in the gnd plane.
> Or doesn't is matter when we got 2 planes ?
>
> It's a 4 layer processorboard with a power plane and a GND plane,
> planespacing is 40 mills, risetime arround 1nS.
> The stackup will be:
>
> Toplayer: Components / Routing
> Inner1: GND plane
> Inner2: Vcc plane
> Bottomlayer: Routing
>
>
> Best Regards,
>
> Johnni Friis
> Gaasdal Bygningsindustri A/S
> Decoration & Sunscreening, Electrics and Shutters
> Baekgaardsvej 40
> DK 6900 Skjern
> E-mail: johnni.friis@xxxxxxxxx
> Phone +45 9980 6666
> Fax +45 9980 6260
>
>
>
> Zhiping Yang
> <zhiping@xxxxxxxx To: si-list@xxxxxxxxxxxxx
> m> cc:
> bcc:
> Sent by:
> si-list-bounce@fr Subject: [SI-LIST] Re:
decoupling
> eelists.org
>
>
> 19-07-2001 19:46
> Please respond to
> si-list
>
>
>
>
>
>
> Hi,
>
> Here is my $0.02 input.
>
> Where to put the decoupling caps is a complicated problem.
> The PCB stackup is a big factor to consider. No matter where
> you put it, the goal is to minimize the total loop inductance
> between IC and caps.
>
> Here is what I would recommend:
> 1. If you can place IC and caps pretty near each other, then
> placing them on the same side is better than the opposite side.
> 2. If IC and caps are on the same side and the power layer is near IC,
> then it's better to place cap near GND pin. If the ground layer is
> near IC, then it is better to place cap near power pin. Here is a plot
> of suggested placement
>
> - IC - -cap-
> | | | |
> --*----------*------- GND
> | |
> ------*--*-----------PWR
>
> 3. I would recommend to connect IC and cap PWR/GND pins directly
> to PWR/GND layer through vias.
>
> Thanks.
>
>
>
> johnni.friis@xxxxxxxxx wrote:
>
> > Hi folks
> >
> > Where do you place the caps ?
> > The caps and the IC is on the side of the PCB, or ?
> >
> > 1. Close to Vcc pin
> > The GND connection of the IC and the cap are made directly to GND-plane=
> > .
> > The Vcc connection is made from Vcc pin to cap to via plane. (See below=
> > ).
> >
> > ___
> > Vcc pin o-----| |----o via to Vcc plane
> > |cap|
> > |___|-----o via to Gnd plane
> >
> > 2. Close to GND pin
> > The Vcc connection of the IC and the cap are made directly to Vcc-plane=
> > .
> > The GND connection is made from GND pin to cap to via to plane. (See
> > below).
> >
> > ___
> > Gnd pin o-----| |----o via to Gnd plane
> > |cap|
> > |___|-----o via to Vcc plane
> >
> > Some say 2 is best. The current from cap to IC will generate a noise
> > voltage in the plane (1. in GND-plane and 2. in Vcc-plane).
> > It's best to have the noise in Vcc-plane.
> > (Our baords is 4 layers, plane seperation of 1 mm (40 mill), F=3D40 M=
> > Hz,
> > singel ended signals, tr/tf ~ 1nS. )
> > What do you think ?
> >
> > Best regards,
> >
> > Johnni Friis
> > G=E5sdal Bygningsindustri A/S
> > Decoration & Sunscreening, Electrics and Shutters
> > B=E6kg=E5rdsvej 40
> > DK 6900 Skjern
> > E-mail: johnni.friis@xxxxxxxxx
> > Phone +45 9980 6666
> > Fax +45 9980 6260=
> >
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>
> --
> Zhiping Yang, Ph. D.
> Hardware Engineer
> Cisco Systems
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