[SI-LIST] Re: decoupling
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 12 Jul 2001 15:38:36 -0600
The list now strips off attachments. For those interested, the material is
covered in Johnson's "Black Magic", pgs 271 - 276.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ken Beach
Sent: Thursday, July 12, 2001 2:19 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: decoupling
Where is the attached word doc.
Ken
-----Original Message-----
From: Ken Cantrell [mailto:Ken.Cantrell@xxxxxxxxxxx]
Sent: Thursday, July 12, 2001 3:05 PM
To: si-list
Subject: [SI-LIST] Re: decoupling
Mark,
Interesting that you are from Xilinx....your company recommends a 2%
regulation instead of a 5% regulation. XAPP158(v1.3) October 4, 2000.
Power supply is Vcc, or Vccint (core), or whatever you are limiting the
voltage sag/ground bounce on. We use abuncha Xilinx parts (reconfiguable
logic/HPC applications). We should be getting eng samples on the
XC2V6000/FG1517 at the end of this month. Attached is a word doc with the
math. Let me know if it still doesn't make sense. Say hi to Austin for me.
He said he was going to present some of the calculations I sent him for an
internal seminar on user issues.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Mark Alexander
Sent: Thursday, July 12, 2001 11:53 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: decoupling
Ken,
I've played around with your equation below, but I'm having trouble getting
anything meaningful out of it. Did this come from a book somewhere that has
an
explanation, or is this your own? If it's the latter, do you have a
derivation?
A couple of specific questions:
is 'powersupply' your VCC voltage?
where did 0.02 come from? Is this 5% variation divided by 2?
Thanks a lot,
mark
Ken Cantrell wrote:
> I use Ztarget = (powersupply*0.02)/di/dt, and have stopped using COGs (ESL
> too high)all together. I use multiple X7Rs to push the frequency out (ala
> the great, but humble....Doug Brooks). Another plug for Doug. If you
> haven't purchased Doug's little software pak (cheeeap!), do it. A real
eye
> opener. Shows the (theoretical) effect of high ESL caps very nicely.
> I haven't had a chance to measure these effects yet (increased emissions,
> discontinuity reflections). Kind of like taking your Mecedes on the Baja
> run. Larry(or anyone), have you had the chance to do so yet?
> Ken
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Khalid Ansari
> Sent: Wednesday, July 11, 2001 10:19 AM
> To: si-list@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: decoupling
>
> Larry,
>
> What happens much above 250 MHz, do we need any more
> capacitors or is the power to ground plane capacitance
> sufficient?
>
> >470 pF 232 MHz
> >0.01 uF 50 MHz
> >0.1 uF 16 MHz
>
> >Putting low ESR capacitors in parallel is like playing with fire. You
> >can cook with fire and heat your house, but if you are not careful with
> >fire, you will get burned. I am a strong advocate of multiple low ESR
> >capacitors in parallel because I believe we have learned how to make
> >good, safe use of them. The optimum power distribution system (fewest
> >components, least cost, least complexity) is obtained from careful
> >selection and placement of capacitors with a reasonably high Q (low
ESR).
> >
> >The trick is to create a low and flat impedance profile in the
> >frequency domain by using different valued capacitors in parallel.
> >Systems behave best when chips look out and see a power distribution
> >system that is resistive in phase (flat impedance). We like to
> >establish a target impedance which is defined as
> >
> >
> >Ztarget = power_supply_voltage * 5% / transient_current.
> >
> >If your PDS impedance meets the target impedance up to the highest
> >frequency of interest, your noise will be within acceptable limits.
> >Much more is written on this topic in
> >
> >"Power Distribution System Design Methodology and Capacitor
> >Selection for Modern CMOS Technology"
> >
> >http://www.qsl.net/wb6tpu/si_documents/docs.html
> >
> >It is easy to meet a 1 Ohm or 0.1 Ohm target impedance using "rules of
> >thumb" for decoupling and high ESR capacitors. It becomes a little
> >more difficult to meet a 10 mOhm target. If you are trying to meet 1
> >mOhm target impedance up to several hundred MHz, it will be very
> >difficult unless you have a well defined methodology and some software
> >tools to help you. On some of our more recent products, at least one
> >of each of the ceramic capacitors from the following menu are used:
> >
> >100uF,
> >47uF, 22uF, 10uF,
> >4.7uF, 2.2uF, 1uF,
> >470nF, 220nF, 100nF,
> >47nF, 22nF, 10nF,
> >4.7nF, 2.2nF, 1nF,
> >680pF, 470pF, 330pF, 220pF, 150pF, 100pF
> >
> >With three capacitors per decade of capacitance, it is possible to make
> >a flat impedance vs frequency profile from about 200 kHz to 400 MHz
> >without any problem from parallel antiresonances. The lower the ESL
> >and ESR (within reason), the fewer components you need. X7R capacitors
> >tend to have Q's between 2 and 5 and three values per decade are
> >sufficient. NPO (COG) capacitors may have Q's between 5 and 10 and six
> >values per decade are useful. Closely spaced power planes may be used
> >instead of some of the pF capacitors.
> >
> >We have our own internal software tools to help manage the design.
> >Cadence is marketing the Power Delivery Tool under SpectraQuest that
> >does the same thing as our tools. The Cadence tool is even better
> >because it is hooked up to the design data base for the PCB.
> >
> >Like all SI tools, these tools are based on models and the analysis is
> >only as good as the models. These days, I spend half of my life out in
> >the lab measuring capacitors and reducing the measured data. The
> >capacitor vendors could help me greatly by measuring the ESR and ESL of
> >their capacitors and publishing the data. They could also help by
> >designing capacitors that have the absolute minimum internal
> >inductance. BTW, traditional measurement techniques do not obtain very
> >good values for ESR and ESL. (Maybe that should be the topic of
> >another email.)
> >
> >regards,
> >Larry Smith
> >Sun Microsystems
>
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