[SI-LIST] Re: What is probability distribution for logic switching
- From: "Kai Keskinen" <kalevi@xxxxxxxxxx>
- To: "Mike Brown" <bmgman@xxxxxxxxxx>
- Date: Fri, 18 Mar 2005 16:43:30 -0500
Mike:
You bring up some excellent points but I think statistics do come into play.
There are still many common clock interfaces out there and you are dealing
with a minimum of 3 chips from usually independent vendors shipped from
various batches over a year or two of production. You have a skew in the
clock to the driver and receiver, you may trigger anywhere in the VinL to
ViH range depending on process variation in the receiver, you have process
variation in the driver chip edge rate, you have variations in the batch to
batch dielectric constant of the PCB layers, etc. Most of the variation in
these things can be represented with some kind of statistical distribution.
Some have narrower spreads (sigmas) and others wider. You also have jitter,
cross-talk and noise but presumably these were taken into account.
So what if you find a negative timing margin when you simulate with IBIS
models over 1 or more corner cases? If it is small, do you ignore it? Do you
tell your manager/customer it will work? Do you say it will work most of the
time but we really don't know for sure about the cold start at below
freezing temperature? How often will they be operating this equipment in a
cold climate in winter? Will people die or loose lots of money if it fails?
How do you figure out the risk?
When you build the prototypes the statistical sample is small even if you
follow a thorough test plan. All the boards were built at the same time from
the same run. The chips were all bought at the same time and presumably come
from the same runs. Your sample meets the requirements but the simulations
don't and no one wants to change the design to make sure it has positive
margins over all process corners? How do you evaluate the chance of failing
timing?
Cheers,
-----Original Message-----
From: Mike Brown [mailto:bmgman@xxxxxxxxxx]
Sent: Thursday, March 17, 2005 7:57 PM
To: kalevi@xxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] What is probability distribution for logic
switching
Kai,
I'm not sure that statistics is a good approach here. It used to be
that a clock-to-clock path often involved multiple chip crossings, and
you could appeal to an RMS delay calculation to pull you out of a
negative slack situation. This appeal is justified by the (presumably)
independent process points of the chips in the path. Most modern
designs take a signal from a source chip and wire it directly to a
destination chip. There's no intervening logic to justify appealing to
a statistical spread.
If you are talking about timing a system, there's little to do except
adjust the vendor's best and worst case numbers for any common-mode
effects: power and/or temperature. This because in general two
different parts on a board can come from different lots (or even
different vendors) at different process extremes. It isn't always easy
to find a Kv or Kt factor to use in this derating. This approach can
give you some comfort in living with the calculated negative slack.
On a single die, not only the power and temperature are common-mode, but
so is the process used to fabricate the die. It is a fact that you
can't get worst case slow and best case fast on the same die in a fixed
environment. The short/fast paths on a worst-case slow PVT die won't be
anywhere best-case fast - but they will not be worst-case slow either.
There's only one vendor that I know of that acknowledges that fact, and
provides timing models that reflect it. That vendor is IBM. Most chip
vendors steadfastly proclaim that the short (early) paths are worst-case
slow, also. I've used a "tracking factor" of 10% to derate the short
paths on a slow PVT, or the long paths on a fast PVT analysis. This is
somewhat of a SWAG, based on some old data I once ran across.
I believe that 0 derating is flat wrong; I've seen data on a GaAs
process stating 17% spread in on-die delay variation (IIRC). I can
justify a perhaps 2% voltage spread and perhaps a 10C variation in Tj
across a die - and that calculates out to a (technology-dependent)
number between 8-15% delay change. I'd guess that 20% or more
adjustment is overly conservative. Pick your poison, or find a vendor
who can support the cross-die timing skew that is present.
Regards
Mike
Kai Keskinen wrote:
>A little question about probability here:
>
>When we do static timing analysis (STA) using simulation tools, we extract
>the flight times with buffer delay compensation for a rising edge with the
>minimum time being when the signal goes through VinL and the maximum time
>being when the signal goes through VinH. Does anyone know what kind of
>probability distribution there is for when the device actually switches?
>Let's assume we are taking about CMOS and use a rising edge as an example.
>Assume no noise or cross-talk, just a nice quiet receiver getting a nice
>clean edge.
>
>Does anyone have a good reference for doing statistical timing analysis?
>What I mean is calculating the likelyhood of a timing failure occurring if
>the STA has shown a negative margin. With the faster clock speeds, we are
>getting more negative margins with one or more corner cases and sometimes,
>there appears to be no reasonable fix to get positive timing for all cases.
>
>Any suggestions will be greatly appreciated.
>
>Kai
>
>
>
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