[SI-LIST] Re: What is probability distribution for logic switching
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 3 Mar 2005 12:01:37 -0500
I'm not an expert here, so take this with a lot of salt.
For delays of silicon devices themselves, I've seen it said that the best-
and worst-case limits are often in the +/- 3-sigma range. Maybe that number
(or my memory of it) is off, and anyway, you don't really know what sort of
statistical distribution you are dealing with. Presumably, it implies that
there is a gaussian distribution to start with, and that most defect-free
devices manufactured fall within this range.
If your devices are "binned" into different speed ranges, then they are
definitely NOT gaussian after being binned.
You could also have devices with multiple internal data paths that don't
look gaussian when combined.
In any event, try asking your silicon vendors if they can tell you anything.
You can get burned if you assume a gaussian distribution that is perfectly
centered between the min and max specs, but the actual parts all come out
all bunched up at the fast or slow end of that range. This can be
especially risky for low volume devices. They aren't going to adjust the
recipe just to center it, if all devices pass or if they have an acceptable
failure rate.
I've heard of production lines where all devices were faster than the min.
delay specs. And IC production lines can change from time to time when they
tweak the formula, or re-spin a part with different technology rules.
I wouldn't apply this kind of statistical variation to interconnect delays,
where you know they really will be what you simulated. (Or worse than you
simulated, including crosstalk.)
The other thing you can do is start measuring your boards, to get a handle
on how well your simulations and analyses compare with reality.
And if you do accept some probability of failures, make sure your quality
control is such that you find as many of them as you can before selling
them.
Stephen Zinck brings up a good point that you may be overly conservative if
you don't take a look at the edge rates, versus how the parts are tested and
specified on the data sheet. Parts are usually spec'd at some Vtest and a
particular input edge rate, and that input test signal crosses VinL/VinH
earlier and later than it crosses Vtest. You can adjust for the differences
between your (simulated) edge rates and those on the data sheet, and this
can help buy back a little bit of flight time.
Regards,
Andy
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