[SI-LIST] Re: What is probability distribution for logic switching
- From: Bill Wurst <billw@xxxxxxxxxxx>
- To: kalevi@xxxxxxxxxx
- Date: Tue, 01 Mar 2005 17:50:11 -0500
Kai,
With no noise or cross-talk, there should be no statistical variation
(unless you're talking about temperature, process, and voltage, but even
then, at any particular corner the answer should be deterministic).
I will relate my own unfortunate experience timing a 6Mgate ASIC, which
the vendor guaranteed would work with zero hold margin. We found that a
combination of cross-talk and noise would actually cause the hold time
to go negative, causing bit errors in the device even though all the
margin was zero or positive. The STA couldn't predict this since it
didn't take cross-talk into account. Simultaneous switching analysis
indicated the design was within the vendor limits for the combination of
package and I/O. Later versions of the STA tool did account for
cross-talk effects, but not before we were forced into an expensive
redesign, where we implemented a minimum margin of 100ps hold margin and
increased the amount of setup margin.
The moral of the story is don't cast silicon without some margin. Even
if you're working with an FPGA, you'll waste a lot of time in the lab
wondering where those bit errors are coming from unless you fix the
problem in the design first.
-Bill
=================
Kai Keskinen wrote:
>A little question about probability here:
>
>When we do static timing analysis (STA) using simulation tools, we extract
>the flight times with buffer delay compensation for a rising edge with the
>minimum time being when the signal goes through VinL and the maximum time
>being when the signal goes through VinH. Does anyone know what kind of
>probability distribution there is for when the device actually switches?
>Let's assume we are taking about CMOS and use a rising edge as an example.
>Assume no noise or cross-talk, just a nice quiet receiver getting a nice
>clean edge.
>
>Does anyone have a good reference for doing statistical timing analysis?
>What I mean is calculating the likelyhood of a timing failure occurring if
>the STA has shown a negative margin. With the faster clock speeds, we are
>getting more negative margins with one or more corner cases and sometimes,
>there appears to be no reasonable fix to get positive timing for all cases.
>
>Any suggestions will be greatly appreciated.
>
>Kai
>
>
>
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